Tetsufumi Tanamoto

Publication Activity (10 Years)

Years Active: 2004-2020
Publications (10 Years): 7

Top Topics

Random Access Memory

Random Number Generator

Simulation Models

Container Terminal

Top Venues

IEICE Electron. Express

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Tetsufumi Tanamoto, Chika Tanaka, Shinichi Takagi
SPICE simulation of 32-kHz crystal-oscillator operation based on Si tunnel FET. IEICE Electron. Express 17 (6) (2020)
Tetsufumi Tanamoto, Chika Tanaka, Satoshi Takaya, Masato Koyama
SPICE simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation. IEICE Electron. Express 15 (3) (2018)
Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita
Physically Unclonable Function Using an Initial Waveform of Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs (7) (2017)
Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani
Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. CoRR (2017)
Tetsufumi Tanamoto, Chika Tanaka, Satoshi Takaya, Masato Koyama
SPICE Simulation of tunnel FET aiming at 32 kHz crystal-oscillator operation. CoRR (2017)
Tetsufumi Tanamoto, Shinichi Yasuda, Satoshi Takaya, Shinobu Fujita
Physically Unclonable Function using Initial Waveform of Ring Oscillators. CoRR (2016)
Tetsufumi Tanamoto, Naoharu Shimomura, Sumio Ikegawa, Mari Matsumoto, Shinobu Fujita, Hiroaki Yoda
High-Speed Magnetoresistive Random-Access Memory Random Number Generator Using Error-Correcting Code. CoRR (2016)
Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. VLSIC (2014)
Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito
Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET CoRR (2011)
Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). FPGA (2010)
Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto
Perspectives and Issues in 3D-IC from Designers' Point of View. ISCAS (2009)
Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita
Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application. ISSCC (2008)
Benjamin Gojman, Raphael Rubin, Concetta Pilotto, André DeHon, Tetsufumi Tanamoto
3D Nanowire-Based Programmable Logic. Nano-Net (2006)
Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita
Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation. ISVLSI (2006)
Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita
Physical random number generators for cryptographic application in mobile devices. ESSCIRC (2005)
Shinichi Yasuda, Hideki Satake, Tetsufumi Tanamoto, Ryuji Ohba, Ken Uchida, Shinobu Fujita
Physical random number generator based on MOS structure after soft breakdown. IEEE J. Solid State Circuits 39 (8) (2004)