Keiko Abe

Publication Activity (10 Years)

Years Active: 2005-2017
Publications (10 Years): 2

Top Topics

Single Processor

Energy Efficiency

Memory Hierarchy

Top Venues

Publications

Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
Novel memory hierarchy with e-STT-MRAM for near-future applications. VLSI-DAT (2017)
Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC (2016)
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. ISSCC (2015)
Teruyoshi Hishiki, Hiroki Yasui, Yoshiko Matsunaga, Megumi Itoshima, Keiko Abe, Takahiko Norose, Takuro Tamura
Pictogram-based tablet application enabling patient input of emotions and behaviors. AMIA (2014)
Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe
Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". ASP-DAC (2014)
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ISIC (2014)
Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE (2013)
Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita
Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. IPDPS Workshops (2012)
Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). FPGA (2010)
Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima
Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies. ISCAS (2010)
Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto
Perspectives and Issues in 3D-IC from Designers' Point of View. ISCAS (2009)
Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2007)
Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
3D on-chip networking technology based on post-silicon devices for future networks-on-chip. Nano-Net (2006)
Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. Nano-Net (2006)
Shinichi Yasuda, Tetsufumi Tanamoto, Ryuji Ohba, Keiko Abe, Hanae Nozaki, Shinobu Fujita
Physical random number generators for cryptographic application in mobile devices. ESSCIRC (2005)