7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture.
Hiroki NoguchiKazutaka IkegamiKeiichi KushidaKeiko AbeShogo ItaiSatoshi TakayaNaoharu ShimomuraJunichi ItoAtsushi KawasumiHiroyuki HaraShinobu FujitaPublished in: ISSCC (2015)
Keyphrases
- hard disk
- design considerations
- random access
- main memory
- read write
- memory access
- data storage
- storage devices
- random access memory
- secondary storage
- flash memory
- high speed
- memory requirements
- times faster
- processing elements
- memory hierarchy
- management system
- memory management
- embedded systems
- ad hoc networks
- file system
- data structure
- dynamic random access memory