Kazutaka Ikegami

Publication Activity (10 Years)

Years Active: 2008-2019
Publications (10 Years): 3

Top Topics

Memory Hierarchy

Highly Reliable

Top Venues

IPDPS Workshops

Publications

Shinobu Fujita, Satoshi Takaya, Susumu Takeda, Kazutaka Ikegami
Circuit And Systems Based on Advanced MRAM for Near Future Computing Applications. VLSI Circuits (2019)
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
Novel memory hierarchy with e-STT-MRAM for near-future applications. VLSI-DAT (2017)
Hiroki Noguchi, Kazutaka Ikegami, Satoshi Takaya, Eishi Arima, Keiichi Kushida, Atsushi Kawasumi, Hiroyuki Hara, Keiko Abe, Naoharu Shimomura, Junichi Ito, Shinobu Fujita, Takashi Nakada, Hiroshi Nakamura
7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write / read-modify-write scheme. ISSCC (2016)
Hiroki Noguchi, Kazutaka Ikegami, Keiichi Kushida, Keiko Abe, Shogo Itai, Satoshi Takaya, Naoharu Shimomura, Junichi Ito, Atsushi Kawasumi, Hiroyuki Hara, Shinobu Fujita
7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture. ISSCC (2015)
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ISIC (2014)
Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. VLSIC (2014)
Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita
Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. IPDPS Workshops (2012)
Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito
Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET CoRR (2011)
Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita
High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only). FPGA (2010)
Mari Matsumoto, Shinichi Yasuda, Ryuji Ohba, Kazutaka Ikegami, Tetsufumi Tanamoto, Shinobu Fujita
Physical Random-Number Generators Based on SiN MOSFET for Secure Smart-Card Application. ISSCC (2008)