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Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures.
Shinobu Fujita
Hiroki Noguchi
Kazutaka Ikegami
Susumu Takeda
Kumiko Nomura
Keiko Abe
Published in:
ISIC (2014)
Keyphrases
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parallel algorithm
design considerations
parallel computers
higher level
parallel architectures
database systems
general purpose
high speed
shared memory
coarse grained
distributed memory
highly parallel
single processor
array processor