Kumiko Nomura

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 5

Top Topics

Memory Hierarchy

Biologically Inspired

Single Processor

Top Venues

Publications

Kumiko Nomura, Yoshifumi Nishi
Synchronized Stepwise Control of Firing and Learning Thresholds in a Spiking Randomly Connected Neural Network toward Hardware Implementation. CoRR (2024)
Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Kumiko Nomura, Koichi Mizushima, Yoshifumi Nishi
Dynamic Firing on Static Analog/Digital Neuron Circuits with Resistive Synapses for Time-Series Neural Network. ISCAS (2020)
Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Radu Berdan, Kumiko Nomura, Yoshifumi Nishi
Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning. ISCAS (2019)
Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi
Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays. ISCAS (2018)
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
Novel memory hierarchy with e-STT-MRAM for near-future applications. VLSI-DAT (2017)
Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe
Novel nonvolatile memory hierarchies to realize "normally-off mobile processors". ASP-DAC (2014)
Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. ISIC (2014)
Hiroki Noguchi, Kumiko Nomura, Keiko Abe, Shinobu Fujita, Eishi Arima, Kyundong Kim, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura
D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory. DATE (2013)
Kazutaka Ikegami, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Masato Oda, Shinobu Fujita
Designing Nonvolatile Reconfigurable Switch-based FPGA through Overall Circuit Performance Evaluation. IPDPS Workshops (2012)
Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima
Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies. ISCAS (2010)
Satoshi Tayu, Kumiko Nomura, Shuichi Ueno
On the two-dimensional orthogonal drawing of series-parallel graphs. Discret. Appl. Math. 157 (8) (2009)
Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto
Perspectives and Issues in 3D-IC from Designers' Point of View. ISCAS (2009)
Satoshi Tayu, Kumiko Nomura, Shuichi Ueno
On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract). ISCAS (2008)
Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
3-D Nanoarchitectures With Carbon Nanotube Mechanical Switches for Future On-Chip Network Beyond CMOS Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2007)
Shinobu Fujita, Kumiko Nomura, Keiko Abe, Thomas H. Lee
3D on-chip networking technology based on post-silicon devices for future networks-on-chip. Nano-Net (2006)
Kumiko Nomura, Keiko Abe, Shinobu Fujita, André DeHon
Novel Design of Three-Dimensional Crossbar for Future Network on Chip based on Post-Silicon Devices. Nano-Net (2006)
Satoshi Tayu, Kumiko Nomura, Shuichi Ueno
On the two-dimensional orthogonal drawing of series-parallel graphs. ISCAS (2006)
Kumiko Nomura, Satoshi Tayu, Shuichi Ueno
On the Orthogonal Drawing of Outerplanar Graphs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2005)
Kumiko Nomura, Satoshi Tayu, Shuichi Ueno
On the Orthogonal Drawing of Outerplanar Graphs. COCOON (2004)
Toshinori Yamada, Kumiko Nomura, Shuichi Ueno
Sparse networks tolerating random faults. Discret. Appl. Math. 137 (2) (2004)
Toshinori Yamada, Kumiko Nomura, Shuichi Ueno
Optimal adaptive parallel diagnosis for arrays. ISCAS (3) (2003)
Kumiko Nomura, Toshinori Yamada, Shuichi Ueno
On Adaptive Fault Diagnosis for Multiprocessor Systems. ISAAC (2001)