Takao Marukame

Publication Activity (10 Years)

Years Active: 2007-2020
Publications (10 Years): 10

Top Topics

Contrastive Divergence

Cmos Technology

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Kumiko Nomura, Koichi Mizushima, Yoshifumi Nishi
Dynamic Firing on Static Analog/Digital Neuron Circuits with Resistive Synapses for Time-Series Neural Network. ISCAS (2020)
Takao Marukame, Toshimitsu Kitamura, Junichi Sugino, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Yoshifumi Nishi
Live Demonstration: Low-Power Static Neural Network Circuits for Long-Term Change Detection. ISCAS (2019)
Takao Marukame, Junichi Sugino, Toshimitsu Kitamura, Kazuo Ishikawa, Koji Takahashi, Yutaka Tamura, Radu Berdan, Kumiko Nomura, Yoshifumi Nishi
Nonlinear Operation of Static-Binary Neuron Circuits and Dynamic Memristive Devices for STDP Learning. ISCAS (2019)
Takao Marukame, Kumiko Nomura, Mari Matusmoto, Satoshi Takaya, Yoshifumi Nishi
Proposal, analysis and demonstration of Analog/Digital-mixed Neural Networks based on memristive device arrays. ISCAS (2018)
Takao Marukame, Yutaka Tamura, Koji Takahashi, Toshimitsu Kitamura, Takashi Takebayashi, Yoshifumi Nishi
Live Demonstration: A prototype of Analog/Digital-mixed Neural Networks for reconfigurable learning. ISCAS (2018)
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. ISCAS (2017)
Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. IEEE Trans. Circuits Syst. II Express Briefs (4) (2017)
Tetsufumi Tanamoto, Satoshi Takaya, Nobuaki Sakamoto, Hirotsugu Kasho, Shinichi Yasuda, Takao Marukame, Shinobu Fujita, Yuichiro Mitani
Physically unclonable function using initial waveform of ring oscillators on 65 nm CMOS technology. CoRR (2017)
Takao Marukame, Alexandre Schmid
Bit-flipping LDPC under noise conditions and its application to physically unclonable functions. ISCAS (2016)
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. ISCAS (2016)
Tetsufumi Tanamoto, Hideyuki Sugiyama, Tomoaki Inokuchi, Takao Marukame, Mizue Ishikawa, Kazutaka Ikegami, Yoshiaki Saito
Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET CoRR (2011)
Tetsuya Uemura, Takao Marukame, Ken-ichi Matsuda, Masafumi Yamamoto
Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions. ISMVL (2007)