Tetsuya Asai

ORCID

Publication Activity (10 Years)

Years Active: 1996-2024
Publications (10 Years): 40

Top Venues

IEICE Trans. Inf. Syst.

Int. J. Parallel Emergent Distributed Syst.

ReConFig

CANDAR

Publications

Yuki Abe, Kohei Nishida, Kota Ando, Tetsuya Asai
SPCTRE: sparsity-constrained fully-digital reservoir computing architecture on FPGA. Int. J. Parallel Emergent Distributed Syst. 39 (2) (2024)
Taisei Saito, Kota Ando, Tetsuya Asai
Extending Binary Neural Networks to Bayesian Neural Networks with Probabilistic Interpretation of Binary Weights. IEICE Trans. Inf. Syst. 107 (8) (2024)
Megumi Akai-Kasaya, Yuki Takeshima, Shaohua Kan, Kohei Nakajima, Takahide Oya, Tetsuya Asai
Performance of reservoir computing in a random network of single-walled carbon nanotubes complexed with polyoxometalate. Neuromorph. Comput. Eng. 2 (1) (2022)
Yafei Ou, Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark. IEEE Trans. Circuits Syst. Video Technol. 32 (5) (2022)
Yoshiharu Yamagishi, Tatsuya Kaneko, Megumi Akai-Kasaya, Tetsuya Asai
Holmes: A Hardware-Oriented Optimizer Using Logarithms. IEICE Trans. Inf. Syst. (12) (2022)
Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda
A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. Int. J. Netw. Comput. 10 (2) (2020)
Prasoon Ambalathankandy, Masayuki Ikebe, Takayuki Yoshida, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA. IEEE Trans. Circuits Syst. Video Technol. 30 (9) (2020)
Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. DICTA (2019)
Tatsuya Kaneko, Hiroshi Momose, Tetsuya Asai
An FPGA Accelerator for Embedded Microcontrollers Implementing a Ternarized Backpropagation Algorithm. ReConFig (2019)
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. IEICE Trans. Inf. Syst. (12) (2019)
Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. CANDAR (2019)
Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
DeltaNet: Differential Binary Neural Network. ASAP (2019)
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. (12) (2019)
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. FPT (2018)
Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. VCIP (2018)
Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. MCSoC (2018)
Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. ICASSP (2018)
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53 (4) (2018)
Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. Microprocess. Microsystems 61 (2018)
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. Complex. 2018 (2018)
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. ISCAS (2017)
Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura
An image sensor/processor 3D stacked module featuring ThruChip interfaces. ASP-DAC (2017)
Makoto Takano, Tetsuya Asai, Takahide Oya
Design and evaluation of single-electron associative memory circuit. Int. J. Parallel Emergent Distributed Syst. 32 (3) (2017)
Enrico Prati, Ernesto Giussani, Giorgio Ferrari, Tetsuya Asai
Noise-assisted transmission of spikes in Maeda-Makino artificial neuron arrays. Int. J. Parallel Emergent Distributed Syst. 32 (3) (2017)
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS (2017)
Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. CANDAR (2017)
Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
Exploring optimized accelerator design for binarized convolutional neural networks. IJCNN (2017)
Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
Quantization Error-Based Regularization in Neural Networks. SGAI Conf. (2017)
Takahide Oya, Tetsuya Asai
Special issue of emerging stochastic computing and hardware. Int. J. Parallel Emergent Distributed Syst. 32 (3) (2017)
Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
Accelerating deep learning by binarized hardware. APSIPA (2017)
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. FPL (2017)
Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura
Low latency divider using ensemble of moving average curves. ISQED (2017)
Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. IEEE Trans. Circuits Syst. II Express Briefs (4) (2017)
Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
A Time-Division Multiplexing Ising Machine on FPGAs. HEART (2017)
Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. ESSCIRC (2016)
Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, Masato Motomura
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata. Int. J. Unconv. Comput. 12 (2-3) (2016)
Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. ReConFig (2016)
Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. APCCAS (2016)
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. ISCAS (2016)
Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. ReConFig (2016)
Kamal El-Sankary, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. IEEE Trans. Circuits Syst. II Express Briefs (8) (2015)
Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. VLSIC (2015)
Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
Enhancing Memcached by Caching Its Data and Functionalities at Network Interface. J. Inf. Process. 23 (2) (2015)
Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
Caching memcached at reconfigurable network interface. FPL (2014)
Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
Achieving higher performance of memcached by caching at network interface. FPT (2014)
Hiroyuki Otake, Kazuyoshi Ishimura, Tetsuya Asai, Takahide Oya
Signal Amplification by Circular Single-Electron Oscillator Network with Stochastic Resonance. BICT (2014)
Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura
A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator. A-SSCC (2014)
Lizeth Gonzalez-Carabarin, Tetsuya Asai, Masato Motomura
Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates. IEICE Electron. Express 11 (15) (2014)
Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join. ARC (2013)
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura
A restricted dynamically reconfigurable architecture for low power processors. ReConFig (2013)
Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, Masato Motomura
Exploiting hardware reconfigurability on window join. HPCS (2013)
Katsuki Ohata, Yukitoshi Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. ICECS (2013)
Kazuki Nakada, Keiji Miura, Tetsuya Asai
Dynamical system design for silicon neurons using phase reduction approach. EMBC (2013)
Kazuki Nakada, Keiji Miura, Tetsuya Asai, Hisa-aki Tanaka
Dynamical systems design of nonlinear oscillators using phase reduction approach. APCCAS (2012)
Kazuki Nakada, Keiji Miura, Tetsuya Asai
Silicon neuron design based on phase reduction analysis. SCIS&ISIS (2012)
Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator. Int. J. Unconv. Comput. 7 (1-2) (2011)
Nobuo Akou, Tetsuya Asai, Takeshi Yanagida, Tomoji Kawai, Yoshihito Amemiya
A behavioral model of unipolar resistive RAMs and its application to HSPICE integration. IEICE Electron. Express 7 (19) (2010)
Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya
Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. ICONIP (1) (2010)
Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. IEICE Trans. Electron. (6) (2010)
Takaaki Hirai, Tetsuya Asai, Yoshihito Amemiya
A CMOS Phase-Shift oscillator Based on the conduction of Heat. J. Circuits Syst. Comput. 19 (4) (2010)
Tetsuya Asai, Yuzuru Ohba, Kiyoshi Ohishi, Katsuyuki Majima, Shiro Urushihara, Koichi Kageyama
High performance sensor-less injection force control considering friction phenomenon. AMC (2010)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
hboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. IEEE Trans. Circuits Syst. II Express Briefs (9) (2010)
Shin'ichi Asai, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair. IEICE Trans. Electron. (6) (2010)
Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2009)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. IEEE J. Solid State Circuits 44 (7) (2009)
Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. ISCAS (2009)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop. ESSCIRC (2009)
Akira Utagawa, Tohru Sahashi, Tetsuya Asai, Yoshihito Amemiya
Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2009)
Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution. NanoNet (2009)
Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose
On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. ISCAS (2009)
Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. ICONIP (2) (2009)
Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici
A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation. Int. J. Nanotechnol. Mol. Comput. 1 (2) (2009)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC (2009)
Yuzuru Ohba, Masaki Sazawa, Kiyoshi Ohishi, Tetsuya Asai, Katsuyuki Majima, Yukio Yoshizawa, Koichi Kageyama
Sensorless Force Control for Injection Molding Machine Using Reaction Torque Observer Considering Torsion Phenomenon. IEEE Trans. Ind. Electron. 56 (8) (2009)
Tomoki Iida, Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya
Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers. ICECS (2009)
Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. IJCNN (2009)
Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya
Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. ICONIP (2) (2008)
Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs. IEICE Electron. Express 5 (6) (2008)
Kazuki Nakada, Jun Igarashi, Tetsuya Asai, Katsumi Tateno, Hatsuo Hayashi, Yoshitaka Ohtubo, Tsutomu Miki, Kiyonori Yoshii
Stochastic Synchronization and Array-Enhanced Coherence Resonance in a Bio-inspired Chemical Sensor Array. CSE (2008)
Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2008)
Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. Int. J. Unconv. Comput. 4 (1) (2008)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. ESSCIRC (2008)
Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN (2007)
Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya
A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing 71 (1-3) (2007)
Takahide Oya, Ikuko N. Motoike, Tetsuya Asai
Single-electron Circuits Performing Dendritic Pattern Formation with Nature-Inspired Cellular Automata. Int. J. Bifurc. Chaos 17 (10) (2007)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
CMOS Smart Sensor for Monitoring the Quality of Perishables. IEEE J. Solid State Circuits 42 (4) (2007)
Andrew Kilinga Kikombo, Takahide Oya, Tetsuya Asai, Yoshihito Amemiya
Discrete Dynamical Systems Consisting of Single-electron Circuits. Int. J. Bifurc. Chaos 17 (10) (2007)
Takahide Oya, Tetsuya Asai, Yoshihito Amemiya
A Single-Electron Reaction-Diffusion Device for Computation of a Voronoi Diagram. Int. J. Unconv. Comput. 3 (4) (2007)
Andrew Adamatzky, Christof Teuscher, Tetsuya Asai
Editorial. Int. J. Parallel Emergent Distributed Syst. 22 (2) (2007)
Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) (2007)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS (2007)
Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. Int. J. Bifurc. Chaos 17 (5) (2007)
Youhei Suzuki, Takahiro Takayama, Ikuko N. Motoike, Tetsuya Asai
Striped and Spotted Pattern Generation on Reaction-diffusion Cellular Automata - Theory and LSI Implementation. Int. J. Unconv. Comput. 3 (1) (2007)
Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2007)
Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya
A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. Int. J. Bifurc. Chaos 16 (1) (2006)
Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
Power-supply circuits for ultralow-power subthreshold MOS-LSIs. IEICE Electron. Express 3 (22) (2006)
Kazuhito Yamada, Ikuko N. Motoike, Tetsuya Asai, Yoshihito Amemiya
Design methodologies for compact logic circuits based on collision-based computing. IEICE Electron. Express 3 (13) (2006)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Kazuki Nakada, Tetsuya Asai, Hatsuo Hayashi
Analog Vlsi Implementation of Resonate-and-fire Neuron. Int. J. Neural Syst. 16 (6) (2006)

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Publication Activity (10 Years)

Top Topics

Top Venues

Tetsuya Asai