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An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs.
Yusuke Tsugita
Ken Ueno
Tetsuya Hirose
Tetsuya Asai
Yoshihito Amemiya
Published in:
IEICE Trans. Electron. (2010)
Keyphrases
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low voltage
mixed signal
cmos technology
random access memory
low power
design considerations
power line
circuit design
power consumption
cmos image sensor
power management
high speed
parallel processing
power dissipation
image sensor
real time
leakage current
finite state machines
intelligent tutoring systems