Yoshihito Amemiya

Publication Activity (10 Years)

Years Active: 1994-2011
Publications (10 Years): 0

Publications

Akira Kondou, Masayuki Ikebe, Junichi Motohisa, Yoshihito Amemiya, Eiichi Sano
A 0.6-4.5 GHz inductorless CMOS low noise amplifier with gyrator-C network. ICECS (2011)
Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator. Int. J. Unconv. Comput. 7 (1-2) (2011)
Nobuo Akou, Tetsuya Asai, Takeshi Yanagida, Tomoji Kawai, Yoshihito Amemiya
A behavioral model of unipolar resistive RAMs and its application to HSPICE integration. IEICE Electron. Express 7 (19) (2010)
Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya
Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. ICONIP (1) (2010)
Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. IEICE Trans. Electron. (6) (2010)
Takaaki Hirai, Tetsuya Asai, Yoshihito Amemiya
A CMOS Phase-Shift oscillator Based on the conduction of Heat. J. Circuits Syst. Comput. 19 (4) (2010)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
hboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. IEEE Trans. Circuits Syst. II Express Briefs (9) (2010)
Shin'ichi Asai, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair. IEICE Trans. Electron. (6) (2010)
Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2009)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs. IEEE J. Solid State Circuits 44 (7) (2009)
Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. ISCAS (2009)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Ken Ueno, Tetsuya Asai, Yoshihito Amemiya
A 30-MHz, 90-ppm/°C fully-integrated clock reference generator with frequency-locked loop. ESSCIRC (2009)
Akira Utagawa, Tohru Sahashi, Tetsuya Asai, Yoshihito Amemiya
Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2009)
Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution. NanoNet (2009)
Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose
On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. ISCAS (2009)
Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya
Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. ICONIP (2) (2009)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC (2009)
Tomoki Iida, Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya
Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers. ICECS (2009)
Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. IJCNN (2009)
Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya
Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. ICONIP (2) (2008)
Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
Temperature-compensated CMOS current reference circuit for ultralow-power subthreshold LSIs. IEICE Electron. Express 5 (6) (2008)
Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2008)
Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. Int. J. Unconv. Comput. 4 (1) (2008)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
A 0.3μW, 7 ppm/°C CMOS Voltage reference circuit for on-chip process monitoring in analog circuits. ESSCIRC (2008)
Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN (2007)
Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya
A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing 71 (1-3) (2007)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
CMOS Smart Sensor for Monitoring the Quality of Perishables. IEEE J. Solid State Circuits 42 (4) (2007)
Andrew Kilinga Kikombo, Takahide Oya, Tetsuya Asai, Yoshihito Amemiya
Discrete Dynamical Systems Consisting of Single-electron Circuits. Int. J. Bifurc. Chaos 17 (10) (2007)
Takahide Oya, Tetsuya Asai, Yoshihito Amemiya
A Single-Electron Reaction-Diffusion Device for Computation of a Voronoi Diagram. Int. J. Unconv. Comput. 3 (4) (2007)
Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) (2007)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS (2007)
Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. Int. J. Bifurc. Chaos 17 (5) (2007)
Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2007)
Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya
A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. Int. J. Bifurc. Chaos 16 (1) (2006)
Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
Power-supply circuits for ultralow-power subthreshold MOS-LSIs. IEICE Electron. Express 3 (22) (2006)
Kazuhito Yamada, Ikuko N. Motoike, Tetsuya Asai, Yoshihito Amemiya
Design methodologies for compact logic circuits based on collision-based computing. IEICE Electron. Express 3 (13) (2006)
Yoshihito Amemiya
Single-Electron Logic Systems Based on a Graphical Representation of Digital Functions. IEICE Trans. Electron. (11) (2006)
Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya
Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model. Int. J. Unconv. Comput. 1 (2) (2005)
Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2005)
Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya
Ultralow-Power Current Reference Circuit with Low Temperature Dependence. IEICE Trans. Electron. (6) (2005)
Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya
A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. 20 (1) (2005)
Takahide Oya, Tetsuya Asai, Takashi Fukui, Yoshihito Amemiya
Reaction-Diffusion Systems Consisting of Single-Electron Oscillators. Int. J. Unconv. Comput. 1 (2) (2005)
Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. ISCAS (3) (2005)
Takahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya
On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electron. Express 2 (3) (2005)
Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici
Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. ISCAS (3) (2005)
Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electron. Express 1 (4) (2004)
Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. IEICE Electron. Express 1 (9) (2004)
Yusuke Kanazawa, Tetsuya Asai, Masayuki Ikebe, Yoshihito Amemiya
A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection. Int. J. Robotics Autom. 19 (4) (2004)
Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. ISCAS (3) (2004)
Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
Biologically-Inspired Locomotion Controller for a Quadruped Walking Robot: Analog IC Implementation of a CPG-Based Controller. J. Robotics Mechatronics 16 (4) (2004)
Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
Design of an Artificial Central Pattern Generator with Feedback Controller. Intell. Autom. Soft Comput. 10 (2) (2004)
Yusuke Kanazawa, Tetsuya Asai, Yoshihito Amemiya
Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses. J. Robotics Mechatronics 15 (2) (2003)
Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya
An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion. IEEE Trans. Neural Networks 14 (5) (2003)
Tetsuya Asai, Yoshihito Amemiya
Biomorphic Analog Devices based on Reaction-Diffusion Systems. ISMVL (2003)
Tetsuya Asai, Yusuke Kanazawa, Yoshihito Amemiya
A subthreshold MOS neuron circuit based on the Volterra system. IEEE Trans. Neural Networks 14 (5) (2003)
Tetsuya Asai, Yuusaku Nishimiya, Yoshihito Amemiya
A CMOS Reaction-Diffusion Circuit Based on Cellular-Automaton Processing Emulating the Belousov-Zhabotinsky Reaction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2002)
Yusuke Kanazawa, Takashi Yamada, Tetsuya Asai, Yoshihito Amemiya
A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. SMC (2002)
Tetsuya Asai, Masato Koutani, Yoshihito Amemiya
An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. IJCNN (3) (2000)
Masayuki Ikebe, Masamichi Akazawa, Yoshihito Amemiya
nu-MOS cellular-automaton devices for intelligent image sensors. KES (3) (1998)
Takashi Morie, Yoshihito Amemiya
An all-analog expandable neural network LSI with on-chip backpropagation learning. IEEE J. Solid State Circuits 29 (9) (1994)