Yusuke Kanazawa

Publication Activity (10 Years)

Years Active: 2002-2009
Publications (10 Years): 0

Publications

Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Kunihiko Iizuka
A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS. IEEE J. Solid State Circuits 44 (6) (2009)
Xuefeng Chen, Yan Wang, Yoshihisa Fujimoto, Pascal Lo Ré, Yusuke Kanazawa, Jesper Steensgaard, Gabor C. Temes
A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications. CICC (2007)
Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Masayuki Miyamoto
An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers. ISSCC (2006)
Yusuke Kanazawa, Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto
A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique. CICC (2006)
Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya
Analog Reaction-Diffusion Chip Imitating Belousov-Zhabotinsky Reaction with Hardware Oregonator Model. Int. J. Unconv. Comput. 1 (2) (2005)
Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electron. Express 1 (4) (2004)
Yusuke Kanazawa, Tetsuya Asai, Masayuki Ikebe, Yoshihito Amemiya
A Novel CMOS Circuit for Depressing Synapse and its Application to Contrast-Invariant Pattern Classification and Synchrony Detection. Int. J. Robotics Autom. 19 (4) (2004)
Yusuke Kanazawa, Tetsuya Asai, Yoshihito Amemiya
Basic Circuit Design of a Neural Processor: Analog CMOS Implementation of Spiking Neurons and Dynamic Synapses. J. Robotics Mechatronics 15 (2) (2003)
Tetsuya Asai, Yusuke Kanazawa, Yoshihito Amemiya
A subthreshold MOS neuron circuit based on the Volterra system. IEEE Trans. Neural Networks 14 (5) (2003)
Yusuke Kanazawa, Takashi Yamada, Tetsuya Asai, Yoshihito Amemiya
A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. SMC (2002)