A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS.
Yoshihisa FujimotoYusuke KanazawaPascal Lo RéKunihiko IizukaPublished in: IEEE J. Solid State Circuits (2009)
Keyphrases
- cmos technology
- nm technology
- low power
- power consumption
- signal to noise ratio
- high speed
- single chip
- silicon on insulator
- parallel processing
- low voltage
- wireless communication systems
- low cost
- analog to digital converter
- power dissipation
- clock frequency
- noise reduction
- mixed signal
- metal oxide semiconductor
- image sensor
- noise ratio
- sampling rate
- hd video
- wide dynamic range
- video streaming
- bit error rate
- cmos image sensor
- wireless networks
- dynamic range