Yoshihisa Fujimoto

Publication Activity (10 Years)

Years Active: 2000-2009
Publications (10 Years): 0

Publications

Yoshihisa Fujimoto
Herman Rings of Blaschke Products of Degree 3. Int. J. Bifurc. Chaos 19 (1) (2009)
Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Kunihiko Iizuka
A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS. IEEE J. Solid State Circuits 44 (6) (2009)
Xuefeng Chen, Yan Wang, Yoshihisa Fujimoto, Pascal Lo Ré, Yusuke Kanazawa, Jesper Steensgaard, Gabor C. Temes
A 18 mW CT ΔΣ modulator with 25 MHz bandwidth for next generation wireless applications. CICC (2007)
Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Masayuki Miyamoto
An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers. ISSCC (2006)
Yusuke Kanazawa, Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto
A 100-MS/s 4-MHz Bandwidth 77.3-dB SNDR ΔΣ ADC with a Triple Sampling Technique. CICC (2006)
Yoshihisa Fujimoto, Pascal Lo Ré, Masayuki Miyamoto
A delta-sigma modulator for a 1-bit digital switching amplifier. IEEE J. Solid State Circuits 40 (9) (2005)
Pascal Lo Ré, Yoshihisa Fujimoto, Hitoshi Tani, Masayuki Miyamoto
A delta-sigma modulator for 1-bit digital switching amplifier [audio power amplifier]. CICC (2004)
Yoshihisa Fujimoto, Hitoshi Tani, Masahiko Maruyama, Hiroyuki Akada, Hiroaki Ogawa, Masayuki Miyamoto
A low-power switched-capacitor variable gain amplifier. IEEE J. Solid State Circuits 39 (7) (2004)
Hitoshi Tani, Yoshihisa Fujimoto, Masahiko Maruyama, Hiroyuki Akada, Hiroaki Ogawa, Masayuki Miyamoto
A low power sample-and-hold amplifier. ESSCIRC (2003)
Masato Koutani, Yoshihisa Fujimoto, Masayuki Miyamoto
A highly linear CMOS buffer circuit with an adjustable output impedance. CICC (2003)
Kunihiko Iizuka, Masayuki Miyamoto, Yoshiji Ohta, Takahiro Suyama, Keita Hara, Shuichi Kawama, Hirofumi Matsui, Shin'ichiro Azuma, Shigenari Taguchi, Yoshihisa Fujimoto, Daniel Senderowicz
CDMA functional blocks using recycling integrator correlators-matched filters and delay-locked loops. IEEE J. Solid State Circuits 36 (3) (2001)
Yoshihisa Fujimoto, Shuichi Kawama, Kunihiko Iizuka, Masayuki Miyamoto, Daniel Senderowicz
A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator. CICC (2000)