A highly linear CMOS buffer circuit with an adjustable output impedance.

Masato Koutani Yoshihisa Fujimoto Masayuki Miyamoto

Published in: CICC (2003)

Keyphrases

circuit design
high speed
analog vlsi
shift register
delay insensitive
vlsi circuits
low voltage
cmos technology
digital circuits
low cost
data sets
buffer size
power supply
power consumption
low power
steady state
buffer overflow