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A 2-V 3.7-mW delay locked-loop using recycling integrator correlators for a 5-Mcps DS-CDMA demodulator.

Yoshihisa FujimotoShuichi KawamaKunihiko IizukaMasayuki MiyamotoDaniel Senderowicz
Published in: CICC (2000)
Keyphrases
  • ds cdma
  • code division multiple access
  • power consumption
  • matched filter
  • mc cdma
  • bit error rate
  • image data