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Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits.
Taichi Ogawa
Tetsuya Hirose
Tetsuya Asai
Yoshihito Amemiya
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2009)
Keyphrases
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floating gate
delay insensitive
threshold selection
neural network