Koichiro Furuta

Publication Activity (10 Years)

Years Active: 1996-2013
Publications (10 Years): 0

Top Topics

Reconfigurable Hardware

Stream Processing

Dimensionality Reduction

Top Venues

Publications

Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join. ARC (2013)
Takao Toi, Noritsugu Nakamura, Taro Fujii, Toshiro Kitaoka, Katsumi Togawa, Koichiro Furuta, Toru Awashima
Optimizing time and space multiplexed computation in a dynamically reconfigurable processor. FPT (2013)
Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Masato Motomura, Koichiro Furuta
Test compression for dynamically reconfigurable processors. ACM Trans. Reconfigurable Technol. Syst. 4 (4) (2011)
Hiroaki Inoue, Junya Yamada, Hideyuki Yoneda, Katsumi Togawa, Koichiro Furuta
Test Compression for Dynamically Reconfigurable Processors. FPL (2010)
Koichiro Furuta, Taro Fujii, Masato Motomura, Kazutoshi Wakabayashi, Masakazu Yamashina
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI. CICC (2000)
Yuichiro Shibata, Masaki Uno, Hideharu Amano, Koichiro Furuta, Taro Fujii, Masato Motomura
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. FCCM (2000)
Masayuki Mizuno, Yasushi Ooi, Naoya Hayashi, Junichi Goto, Masatoshi Hozumi, Koichiro Furuta, Atsufumi Shibayama, Yoetsu Nakazawa, Osamu Ohnishi, Shu-Yu Zhu, Yutaka Yokoyama, Yoichi Katayama, Hideto Takano, Noriyuki Miki, Yuzo Senda, Ichiro Tamitani, Masakazu Yamashina
A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking. IEEE J. Solid State Circuits 32 (11) (1997)
Masayuki Mizuno, Masakazu Yamashina, Koichiro Furuta, Hiroyuki Igura, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Hachiro Yamada
A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE J. Solid State Circuits 31 (6) (1996)