Masato Motomura

ORCID

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 86

Top Venues

ISSCC

IEEE Access

IEEE J. Solid State Circuits

IEICE Trans. Inf. Syst.

Publications

Yuki Ichikawa, Akihiro Shioda, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
An Accurate FPGA-Based ORB Feature Extractor for SLAM with Row-Wise Keypoint Selection. ICCE (2024)
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
Efficient COO to CSR Conversion for Accelerating Sparse Matrix Processing on FPGA. ICCE (2024)
Hikari Otsuka, Yasuyuki Okoshi, Ángel López García-Arias, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Masato Motomura
Restricted Random Pruning at Initialization for High Compression Range. Trans. Mach. Learn. Res. 2024 (2024)
Masato Motomura
RAW 2024 Invited Talk-5. IPDPS (Workshops) (2024)
Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu
Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow. ASPDAC (2024)
Kyo Kuroki, Satoru Jimbo, Thiem Van Chu, Masato Motomura, Kazushi Kawamura
Classical Thermodynamics-based Parallel Annealing Algorithm for High-speed and Robust Combinatorial Optimization. GECCO (2024)
Hikari Otsuka, Daiki Chijiwa, Ángel López García-Arias, Yasuyuki Okoshi, Kazushi Kawamura, Thiem Van Chu, Daichi Fujiki, Susumu Takeuchi, Masato Motomura
Partial Search in a Frozen Network is Enough to Find a Strong Lottery Ticket. CoRR (2024)
Satoru Jimbo, Tatsuhiko Shirai, Nozomu Togawa, Masato Motomura, Kazushi Kawamura
A GPU-Based Ising Machine With a Multi-Spin-Flip Capability for Constrained Combinatorial Optimization. IEEE Access 12 (2024)
Junnosuke Suzuki, Mari Yasunaga, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Progressive Variable Precision DNN With Bitwise Ternary Accumulation. AICAS (2024)
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Pianissimo: A Sub-mW Class DNN Accelerator With Progressively Adjustable Bit-Precision. IEEE Access 12 (2024)
Masato Watanabe, Shungo Kumazawa, Thiem Van Chu, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
Exploration of Hyperdimensional Computing Using Locality-Sensitive Hashing Mechanism on FPGA. ICCE (2024)
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
High Throughput Datapath Design for Vision Permutator FPGA Accelerator. ICCE (2024)
Shungo Kumazawa, Jaehoon Yu, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Toward Improving Ensemble-Based Collaborative Inference at the Edge. IEEE Access 12 (2024)
Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Multicoated and Folded Graph Neural Networks With Strong Lottery Tickets. LoG (2023)
Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. VLSI Technology and Circuits (2023)
Jiale Yan, Hiroaki Ito, Ángel López García-Arias, Yasuyuki Okoshi, Hikari Otsuka, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets. CoRR (2023)
Mari Yasunaga, Junnosuke Suzuki, Masato Watanabe, Kazushi Kawamura, Thiem Van Chu, Jaehoon Yu, Masato Motomura
A Highly Accurate and Parallel Vision MLP FPGA Accelerator based on FP7/8 SIMD Operations. MCSoC (2023)
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control for Various Combinatorial Optimization Problems. IEICE Trans. Inf. Syst. 106 (12) (2023)
Ángel López García-Arias, Yasuyuki Okoshi, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
Recurrent Residual Networks Contain Stronger Lottery Tickets. IEEE Access 11 (2023)
Thiem Van Chu, Yu Mizutani, Yuta Nagahara, Shungo Kumazawa, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
Decision Forest Training Accelerator Based on Binary Feature Decomposition. FCCM (2023)
Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance. COOL CHIPS (2023)
Jiale Yan, Kota Ando, Jaehoon Yu, Masato Motomura
TT-MLP: Tensor Train Decomposition on Deep MLPs. IEEE Access 11 (2023)
Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Anas, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. ISSCC (2023)
Yasuyuki Okoshi, Ángel López García-Arias, Kazutoshi Hirose, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
Multicoated Supermasks Enhance Hidden Networks. ICML (2022)
Yafei Ou, Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
Real-Time Tone Mapping: A Survey and Cross-Implementation Hardware Benchmark. IEEE Trans. Circuits Syst. Video Technol. 32 (5) (2022)
Daiki Okonogi, Satoru Jimbo, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
APC-SCA: A Fully-Parallel Annealing Algorithm with Autonomous Pinning Effect Control. IPDPS Workshops (2022)
Satoru Jimbo, Daiki Okonogi, Kota Ando, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura
A Hybrid Integer Encoding Method for Obtaining High-Quality Solutions of Quadratic Knapsack Problems on Solid-State Annealers. IEICE Trans. Inf. Syst. (12) (2022)
Kazutoshi Hirose, Jaehoon Yu, Kota Ando, Yasuyuki Okoshi, Ángel López García-Arias, Junnosuke Suzuki, Thiem Van Chu, Kazushi Kawamura, Masato Motomura
Hiddenite: 4K-PE Hidden Network Inference 4D-Tensor Engine Exploiting On-Chip Model Construction Achieving 34.8-to-16.0TOPS/W for CIFAR-100 and ImageNet. ISSCC (2022)
Pitchayapatchaya Srikram, Prasoon Ambalathankandy, Yuri Kanazawa, Masato Motomura, Masayuki Ikebe
Ring-VCO-based ReLU activation function with linearity improvement for pulsed neuron circuits. ICECS 2022 (2022)
Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. BMVC (2021)
Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE J. Solid State Circuits 56 (1) (2021)
Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ExtraFerns: Fully Parallel Ensemble Learning Technique with Random Projection and Non-Greedy yet Minimal Memory Access Training. Int. J. Netw. Comput. 11 (2) (2021)
Junnosuke Suzuki, Tomohiro Kaneko, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ProgressiveNN: Achieving Computational Scalability with Dynamic Bit-Precision Adjustment by MSB-first Accumulative Computation. Int. J. Netw. Comput. 11 (2) (2021)
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12: 1 SerDes in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (2) (2021)
Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner. HCS (2021)
Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura
Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks With a Diversified Multi-Exit Architecture. IEEE Access 9 (2021)
Ángel López García-Arias, Masanori Hashimoto, Masato Motomura, Jaehoon Yu
Hidden-Fold Networks: Random Recurrent Residuals Using Sparse Supermasks. CoRR (2021)
Thiem Van Chu, Ryuichi Kitajima, Kazushi Kawamura, Jaehoon Yu, Masato Motomura
A High-Performance and Flexible FPGA Inference Accelerator for Decision Forests Based on Prior Feature Space Partitioning. FPT (2021)
Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda
A Hardware-efficient Weight Sampling Circuit for Bayesian Neural Networks. Int. J. Netw. Comput. 10 (2) (2020)
Kasho Yamamoto, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura
7.3 STATICA: A 512-Spin 0.25M-Weight Full-Digital Annealing Processor with a Near-Memory All-Spin-Updates-at-Once Architecture for Combinatorial Optimization with Complete Spin-Spin Interactions. ISSCC (2020)
Shungo Kumazawa, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ExtraFerns: Fully Parallel Ensemble Learning Technique with Non-Greedy yet Minimal Memory Access Training. CANDAR (2020)
Junnosuke Suzuki, Kota Ando, Kazutoshi Hirose, Kazushi Kawamura, Thiem Van Chu, Masato Motomura, Jaehoon Yu
ProgressiveNN: Achieving Computational Scalability without Network Alteration by MSB-first Accumulative Computation. CANDAR (2020)
Prasoon Ambalathankandy, Masayuki Ikebe, Takayuki Yoshida, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai
An Adaptive Global and Local Tone Mapping Algorithm Implemented on FPGA. IEEE Trans. Circuits Syst. Video Technol. 30 (9) (2020)
Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. ISCAS (2020)
Taiga Ikeda, Kento Sakurada, Atsuyoshi Nakamura, Masato Motomura, Shinya Takamaeda-Yamazaki
Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs. ARC (2020)
Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. DICTA (2019)
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Dither NN: Hardware/Algorithm Co-Design for Accurate Quantized Neural Networks. IEICE Trans. Inf. Syst. (12) (2019)
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS. IEEE J. Solid State Circuits 54 (1) (2019)
Yuki Hirayama, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
A Resource-Efficient Weight Sampling Method for Bayesian Neural Network Accelerators. CANDAR (2019)
Masato Motomura
Foreword. IEICE Trans. Inf. Syst. (5) (2019)
Yuka Oba, Kota Ando, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
DeltaNet: Differential Binary Neural Network. ASAP (2019)
Kasho Yamamoto, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
FPGA-Based Annealing Processor with Time-Division Multiplexing. IEICE Trans. Inf. Syst. (12) (2019)
Yohan Frans, Wim Dehaene, Masato Motomura, Seung-Jun Bae
Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 54 (1) (2019)
Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Dither NN: An Accurate Neural Network with Dithering for Low Bit-Precision Hardware. FPT (2018)
Dejan Markovic, Masato Motomura, Byeong-Gyu Nam
Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee. ISSCC (2018)
Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. VCIP (2018)
Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
Area and Energy Optimization for Bit-Serial Log-Quantized DNN Accelerator with Shared Accumulators. MCSoC (2018)
Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Junichiro Kadomoto, Tomoki Miyata, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura
QUEST: A 7.49TOPS multi-purpose log-quantized DNN inference engine stacked on 96MB 3D SRAM using inductive-coupling technology in 40nm CMOS. ISSCC (2018)
Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai
Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. ICASSP (2018)
Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE J. Solid State Circuits 53 (4) (2018)
Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. VLSI Circuits (2018)
Prasoon Ambalathankandy, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe, Hotaka Kusano
Real-time HDTV to 4K and 8K-UHD conversions using anti-aliasing based super resolution algorithm on FPGA. Microprocess. Microsystems 61 (2018)
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
Protocomputing Architecture over a Digital Medium Aiming at Real-Time Video Processing. Complex. 2018 (2018)
Tomoya Fujii, Simpei Sato, Hiroki Nakahara, Masato Motomura
An FPGA Realization of a Deep Convolutional Neural Network Using a Threshold Neuron Pruning. ARC (2017)
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. ISCAS (2017)
Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura
An image sensor/processor 3D stacked module featuring ThruChip interfaces. ASP-DAC (2017)
Meng-Fan Chang, Jun Deguchi, Vivek De, Masato Motomura, Shinichiro Shiratake, Marian Verhelst
F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systems. ISSCC (2017)
Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
In-memory area-efficient signal streaming processor design for binary neural networks. MWSCAS (2017)
Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
Logarithmic Compression for Memory Footprint Reduction in Neural Network Training. CANDAR (2017)
Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
Exploring optimized accelerator design for binarized convolutional neural networks. IJCNN (2017)
Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
Quantization Error-Based Regularization in Neural Networks. SGAI Conf. (2017)
Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
Accelerating deep learning by binarized hardware. APSIPA (2017)
Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura
A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only). FPGA (2017)
Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. FPL (2017)
Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura
Low latency divider using ensemble of moving average curves. ISQED (2017)
Takao Marukame, Kodai Ueyoshi, Tetsuya Asai, Masato Motomura, Alexandre Schmid, Masamichi Suzuki, Yusuke Higashi, Yuichiro Mitani
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation. IEEE Trans. Circuits Syst. II Express Briefs (4) (2017)
Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
A Time-Division Multiplexing Ising Machine on FPGAs. HEART (2017)
Hiroki Nakahara, Haruyoshi Yonekawa, Tsutomu Sasao, Hisashi Iwamoto, Masato Motomura
A memory-based realization of a binarized deep convolutional neural network. FPT (2016)
Jeffrey C. Gealow, Masato Motomura
Foreword. VLSI Circuits (2016)
Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura
Motion-vector estimation and cognitive classification on an image sensor/processor 3D stacked system featuring ThruChip interfaces. ESSCIRC (2016)
Miho Ushida, Alexandre Schmid, Tetsuya Asai, Kazuyoshi Ishimura, Masato Motomura
Motion Vector Estimation of Textureless Objects Exploiting Reaction-Diffusion Cellular Automata. Int. J. Unconv. Comput. 12 (2-3) (2016)
Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
FPGA architecture for feed-forward sequential memory network targeting long-term time-series forecasting. ReConFig (2016)
Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
A 2-clock-cycle Naïve Bayes classifier for dynamic branch prediction in pipelined RISC microprocessors. APCCAS (2016)
Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid
Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. ISCAS (2016)
Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
An FPGA-optimized architecture of anti-aliasing based super resolution for real-time HDTV to 4K- and 8K-UHD conversions. ReConFig (2016)
Masato Motomura, Andreia Cathelin
Introduction to the Special Issue on the 2015 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 51 (4) (2016)
Jeffrey C. Gealow, Masato Motomura
Introduction to the Special Issue on the 2014 Symposium on VLSI Circuits. IEEE J. Solid State Circuits 50 (4) (2015)
Kamal El-Sankary, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
Crosstalk Rejection in 3-D-Stacked Interchip Communication With Blind Source Separation. IEEE Trans. Circuits Syst. II Express Briefs (8) (2015)
Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
Image sensor/digital logic 3D stacked module featuring inductive coupling channels for high speed/low-noise image transfer. VLSIC (2015)
Li-Chung Hsu, Masato Motomura, Yasuhiro Take, Tadahiro Kuroda
Through Chip Interface Based Three-Dimensional FPGA Architecture Exploration. IEICE Trans. Electron. (4) (2015)
Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
Enhancing Memcached by Caching Its Data and Functionalities at Network Interface. J. Inf. Process. 23 (2) (2015)
Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
Caching memcached at reconfigurable network interface. FPL (2014)
Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura
Achieving higher performance of memcached by caching at network interface. FPT (2014)
Itaru Hida, Dahoo Kim, Tetsuya Asai, Masato Motomura
A 4.5 to 13 times energy-efficient embedded microprocessor with mainly-static/partially-dynamic reconfigurable array accelerator. A-SSCC (2014)
Lizeth Gonzalez-Carabarin, Tetsuya Asai, Masato Motomura
Low-power asynchronous digital pipeline based on mismatch-tolerant logic gates. IEICE Electron. Express 11 (15) (2014)
Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join. ARC (2013)
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura
A restricted dynamically reconfigurable architecture for low power processors. ReConFig (2013)
Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Tetsuya Asai, Masato Motomura
Exploiting hardware reconfigurability on window join. HPCS (2013)
Hiroaki Inoue, Takashi Takenaka, Masato Motomura
C-Based Complex Event Processing on Reconfigurable Hardware. IEEE Trans. Very Large Scale Integr. Syst. 21 (5) (2013)
Katsuki Ohata, Yukitoshi Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
Hardware-oriented stereo vision algorithm based on 1-D guided filtering and its FPGA implementation. ICECS (2013)

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Masato Motomura