Ryota Yasudo

Publication Activity (10 Years)

Years Active: 2014-2024
Publications (10 Years): 34

Top Topics

Gpu Implementation

Maximum Independent Set

Optimization Strategy

Interconnection Networks

Top Venues

Concurr. Comput. Pract. Exp.

Publications

Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano
Power Optimized Design Framework for FPGA Clusters. IPSJ Trans. Syst. LSI Des. Methodol. 17 (2024)
Satoko Iida, Ryota Yasudo
Solving the QAP by Two-Stage Graph Pointer Networks and Reinforcement Learning. CoRR (2024)
Ryota Yasudo
Bandit-based Variable Fixing for Binary Optimization on GPU Parallel Computing. PDP (2023)
Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano
High-throughput FPGA implementation for quadratic unconstrained binary optimization. Concurr. Comput. Pract. Exp. 35 (14) (2023)
Masashi Oda, Kai Keida, Ryota Yasudo
Dual Diagonal Mesh: An Optimal Memory Cube Network Under Geometric Constraints. candar (2023)
Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
Designing low-diameter interconnection networks with multi-ported host-switch graphs. Concurr. Comput. Pract. Exp. 35 (11) (2023)
Tomohiro Imanaga, Koji Nakano, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano
Simple iterative trial search for the maximum independent set problem optimized for the GPUs. Concurr. Comput. Pract. Exp. 35 (14) (2023)
Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase
Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA Clusters. ICFPT (2023)
Kazushi Kawamura, Jaehoon Yu, Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo, Ángel López García-Anas, Kota Ando, Bruno Hideki Fukushima-Kimura, Ryota Yasudo, Thiem Van Chu, Masato Motomura
Amorphica: 4-Replica 512 Fully Connected Spin 336MHz Metamorphic Annealer with Programmable Optimization Strategy and Compressed-Spin-Transfer Multi-Chip Extension. ISSCC (2023)
Ryota Yasudo, Koji Nakano, Yasuaki Ito, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano
GPU-accelerated scalable solver with bit permutated cyclic-min algorithm for quadratic unconstrained binary optimization. J. Parallel Distributed Comput. 167 (2022)
Ryota Yasudo, Koji Nakano, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Shiro Ozaki, Takashi Yazane, Kenichiro Hamano
Graph-theoretic Formulation of QUBO for Scalable Local Search on GPUs. IPDPS Workshops (2022)
Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase
Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure Learning. FPT (2022)
Kohei Ito, Ryota Yasudo, Hideharu Amano
Optimizing Application Mapping for Multi-FPGA Systems with Multi-ejection STDM Switches. FPL (2022)
Tomohiro Imanaga, Koji Nakano, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Shiro Ozaki, Takashi Yazane, Kenichiro Hamano
Solving the sparse QUBO on multiple GPUs for Simulating a Quantum Annealer. CANDAR (2021)
Ryota Yasudo, José Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo
Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms. ACM Trans. Reconfigurable Technol. Syst. 14 (3) (2021)
Takuma Wada, Naoki Matsumura, Ryota Yasudo, Koji Nakano, Yasuaki Ito
Efficient implementations of Bloom filter using block RAMs and DSP slices on the FPGA. Concurr. Comput. Pract. Exp. 33 (12) (2021)
Tomohiro Imanaga, Koji Nakano, Masaki Tao, Ryota Yasudo, Yasuaki Ito, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano
Efficient GPU Implementation for Solving the Maximum Independent Set Problem. CANDAR (2020)
Masaki Tao, Koji Nakano, Yasuaki Ito, Ryota Yasudo, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, Yoko Inaba
A Work-Time Optimal Parallel Exhaustive Search Algorithm for the QUBO and the Ising model, with GPU implementation. IPDPS Workshops (2020)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. (12) (2020)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. (1) (2020)
Ryota Yasudo, Koji Nakano, Yasuaki Ito, Masaru Tatekawa, Ryota Katsuki, Takashi Yazane, Yoko Inaba
Adaptive Bulk Search: Solving Quadratic Unconstrained Binary Optimization Problems on Multiple GPUs. ICPP (2020)
Takeo Hosomi, Ryota Yasudo, Michihiro Koibuchi, Shinji Shimojo
Dual-Plane Isomorphic Hypercube Network. HPC Asia (2020)
Hiroshi Kagawa, Yasuaki Ito, Koji Nakano, Ryota Yasudo, Yuya Kawamata, Ryota Katsuki, Yusuke Tabata, Takashi Yazane, Kenichiro Hamano
Fully-Pipelined Architecture for Simulated Annealing-based QUBO Solver on the FPGA. CANDAR (2020)
Masatoshi Hayashikawa, Koji Nakano, Yasuaki Ito, Ryota Yasudo
Folded Bloom Filter for High Bandwidth Memory, with GPU Implementations. CANDAR (2019)
Ryota Yasudo, Koji Nakano
The Degree Diameter Problem for Host-Switch Graphs. CANDAR Workshops (2019)
Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
Designing High-Performance Interconnection Networks with Host-Switch Graphs. IEEE Trans. Parallel Distributed Syst. 30 (2) (2019)
Ryota Yasudo, José Gabriel F. Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker
Performance Estimation for Exascale Reconfigurable Dataflow Platforms. FPT (2018)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano
k-Optimized Path Routing for High-Throughput Data Center Networks. CANDAR (2018)
Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano
Performance Prediction for Large-Scale Heterogeneous Platforms. FCCM (2018)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. ICPADS (2017)
Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers 66 (4) (2017)
Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. ICPP (2017)
Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. ISPAN-FCST-ISCC (2017)
Hiroshi Nakahara, Ng. Anh Vu Doan, Ryota Yasudo, Hideharu Amano
XYZ-Randomization using TSVs for Low-Latency Energy Efficient 3D-NoCs. NOCS (2017)
Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. NOCS (2015)
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
Design of a low power NoC router using Marching Memory Through type. NOCS (2014)
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
A low power NoC router using the marching memory through type. COOL Chips (2014)