Ryuta Kawano

Publication Activity (10 Years)

Years Active: 2015-2022
Publications (10 Years): 16

Top Topics

Interconnection Networks

Top Venues

IEICE Trans. Inf. Syst.

Publications

Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems 90 (2022)
Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR (2022)
Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT (2021)
Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP (2021)
Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. CANDAR (Workshops) (2020)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. (12) (2020)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. (1) (2020)
Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
Deadlock-Free Layered Routing for Infiniband Networks. CANDAR Workshops (2019)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano
k-Optimized Path Routing for High-Throughput Data Center Networks. CANDAR (2018)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. ICPADS (2017)
Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. IEICE Trans. Inf. Syst. (12) (2017)
Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. IEICE Trans. Inf. Syst. (8) (2017)
Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
A Layout-Oriented Routing Method for Low-Latency HPC Networks. IEICE Trans. Inf. Syst. (12) (2017)
Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. CANDAR (2016)
Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
Body bias grain size exploration for a coarse grained reconfigurable accelerator. FPL (2016)
Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. ICIS (2016)
Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
Optimized Core-Links for Low-Latency NoCs. PDP (2015)