Hayate Okuhara

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 35

Top Topics

Design Automation

Optimization Method

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Takuya Kojima, Yosuke Yanai, Hayate Okuhara, Hideharu Amano, Morihiro Kuga, Masahiro Iida
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks. COOL CHIPS (2024)
Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing. IEEE J. Solid State Circuits 59 (1) (2024)
Francesco Conti, Davide Rossi, Gianna Paulin, Anaelo Garofalo, Alfio Di Mauro, Georg Rutishauer, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini
A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing. ISSCC (2023)
Karim Ali Ahmed, Hayate Okuhara, Massimo Alioto
55pW/pixel Peak Power Imager with Near-Sensor Novelty/Edge Detection and DC-DC Converter-Less MPPT for Purely Harvested Sensor Nodes. ISSCC (2023)
Francesco Conti, Gianna Paulin, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini
Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing. CoRR (2023)
Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano
A Scalable Body Bias Optimization Method Toward Low-Power CGRAs. IEEE Micro 43 (1) (2023)
Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano
Body Bias Control on a CGRA based on Convex Optimization. COOL CHIPS (2022)
Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi
A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 29 (10) (2021)
Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini
A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator With 0.22% INL. IEEE Trans. Circuits Syst. II Express Briefs 68 (1) (2021)
Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi
A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS. CoRR (2021)
Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini
An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. CoRR (2020)
Hayate Okuhara, Ahmed Elnaqib, Davide Rossi, Alfio Di Mauro, Philipp Mayer, Pierpaolo Palestri, Luca Benini
An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. ISCAS (2020)
Ahmed Elnaqib, Hayate Okuhara, Taekwang Jang, Davide Rossi, Luca Benini
A 0.5GHz 0.35mW LDO-Powered Constant-Slope Phase Interpolator with 0.22% INL. CoRR (2020)
Hesam Zolfaghari, Davide Rossi, Walter Cerroni, Hayate Okuhara, Carla Raffaelli, Jari Nurmi
Flexible Software-Defined Packet Processing Using Low-Area Hardware. IEEE Access 8 (2020)
Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Kazusa Musha, Hideharu Amano, Ryuichi Sakamoto, Masaaki Kondo, Mitaro Namiki
A Preliminary Evaluation of Building Block Computing Systems. MCSoC (2019)
Hideto Kayashima, Takuya Kojima, Hayate Okuhara, Tsunaaki Shidei, Hideharu Amano
Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process. CANDAR Workshops (2019)
Hayate Okuhara, Ryosuke Kazami, Hideharu Amano
A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration. MCSoC (2019)
Carlos Cesar Cortes Torres, Hayate Okuhara, Nobuyuki Yamasaki, Hideharu Amano
Analysis of Body Bias Control Using Overhead Conditions for Real Time Systems: A Practical Approach. IEICE Trans. Inf. Syst. (4) (2018)
Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano
Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26 (7) (2018)
Hayate Okuhara, Akram Ben Ahmed, Hideharu Amano
Digitally Assisted On-Chip Body Bias Tuning Scheme for Ultra Low-Power VLSI Systems. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Takuya Kojima, Naoki Ando, Yusuke Matshushita, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano
Real Chip Evaluation of a Low Power CGRA with Optimized Application Mapping. HEART (2018)
Ryosuke Kazami, Hayate Okuhara, Hideharu Amano
Design automation methodology of a critical path monitor for adaptive voltage controls. COOL CHIPS (2018)
Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. MCSoC (2018)
Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano
Optimization of Body Biasing for Variable Pipelined Coarse-Grained Reconfigurable Architectures. IEICE Trans. Inf. Syst. (6) (2018)
Keita Azegami, Hayate Okuhara, Hideharu Amano
Body Bias Control for Renewable Energy Source with a High Inner Resistance. IEEE Trans. Multi Scale Comput. Syst. 4 (4) (2018)
Hayate Okuhara, Yu Fujita, Kimiyoshi Usami, Hideharu Amano
Power Optimization Methodology for Ultralow Power Microcontroller With Silicon on Thin BOX MOSFET. IEEE Trans. Very Large Scale Integr. Syst. 25 (4) (2017)
Takuya Kojima, Naoki Ando, Hayate Okuhara, Hideharu Amano
Glitch-aware variable pipeline optimization for CGRAs. ReConFig (2017)
Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
Body Bias Domain Partitioning Size Exploration for a Coarse Grained Reconfigurable Accelerator. IEICE Trans. Inf. Syst. (12) (2017)
Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano
Leveraging asymmetric body bias control for low power LSI design. COOL Chips (2017)
Nguyen Anh Vu Doan, Yusuke Matsushita, Naoki Ando, Hayate Okuhara, Hideharu Amano
Multi-objective Optimization for Application Mapping and Body Bias Control on a CGRA. MCSoC (2017)
Keita Azegami, Hayate Okuhara, Hideharu Amano
Body bias control for renewable energy source with a high inner resistance. COOL Chips (2017)
Takuya Kojima, Naoki Ando, Hayate Okuhara, Ng. Anh Vu Doan, Hideharu Amano
Body bias optimization for variable pipelined CGRA. FPL (2017)
Johannes Maximilian Kühn, Akram Ben Ahmed, Hayate Okuhara, Hideharu Amano, Oliver Bringmann, Wolfgang Rosenstiel
MuCCRA4-BB: A fine-grained body biasing capable DRP. COOL Chips (2016)
Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano
Body bias grain size exploration for a coarse grained reconfigurable accelerator. FPL (2016)
Naoki Ando, Koichiro Masuyama, Hayate Okuhara, Hideharu Amano
Variable pipeline structure for Coarse Grained Reconfigurable Array CMA. FPT (2016)
Hayate Okuhara, Kimiyoshi Usami, Hideharu Amano
A leakage current monitor circuit using silicon on thin BOX MOSFET for dynamic back gate bias control. COOL Chips (2015)
Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano
A 297mops/0.4mw ultra low power coarse-grained reconfigurable accelerator CMA-SOTB-2. ReConFig (2015)
Yu Fujita, Hayate Okuhara, Koichiro Masuyama, Hideharu Amano
Power Optimization Considering the Chip Temperature of Low Power Reconfigurable Accelerator CMA-SOTB. CANDAR (2015)
Koichiro Masuyama, Yu Fujita, Hayate Okuhara, Hideharu Amano
7MOPS/lemon-battery image processing demonstration with an ultra-low power reconfigurable accelerator CMA-SOTB-2. FPL (2015)
Hayate Okuhara, Kuniaki Kitamori, Yu Fujita, Kimiyoshi Usami, Hideharu Amano
An optimal power supply and body bias voltage for a ultra low power micro-controller with silicon on thin box MOSFET. ISLPED (2015)