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Real Chip Performance Evaluation on Through Chip Interface IP for Renesas SOTB 65nm Process.
Hideto Kayashima
Takuya Kojima
Hayate Okuhara
Tsunaaki Shidei
Hideharu Amano
Published in:
CANDAR Workshops (2019)
Keyphrases
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low cost
high speed
single chip
high density
search engine
sensor networks
circuit design
cmos technology