Hiroki Matsutani

ORCID

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 130

Top Venues

CoRR

IEICE Trans. Inf. Syst.

PDP

CANDAR

Publications

Shin Morishima, Hiroki Matsutani
An Efficient Distributed Reinforcement Learning Architecture for Long-Haul Communication Between Actors and Learner. IEEE Access 12 (2024)
Kazuki Sunaga, Takeya Yamada, Hiroki Matsutani
A Sequential Approach to Detect Drifts and Retrain Neural Networks on Resource-Limited Edge Devices. IEICE Trans. Inf. Syst. 107 (6) (2024)
Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani
Federated Learning of Neural ODE Models with Different Iteration Counts. IEICE Trans. Inf. Syst. 107 (6) (2024)
Yujiro Yahata, Keisuke Sugiura, Hiroki Matsutani
A Scalable Secure Fault Tolerant Aggregation for P2P Federated Learning. IPDPS (Workshops) (2024)
Kazuki Sunaga, Keisuke Sugiura, Hiroki Matsutani
An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm. IPDPS (Workshops) (2024)
Ikumi Okubo, Keisuke Sugiura, Hiroki Matsutani
A Cost-Efficient FPGA Implementation of Tiny Transformer Model using Neural ODE. CoRR (2024)
Keisuke Sugiura, Hiroki Matsutani
FPGA-Accelerated Correspondence-free Point Cloud Registration with PointNet Features. CoRR (2024)
Keisuke Sugiura, Hiroki Matsutani
An Integrated FPGA Accelerator for Deep Learning-Based 2D/3D Path Planning. IEEE Trans. Computers 73 (6) (2024)
Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani
Performance Improvement of Federated Learning Server using Smart NIC. CANDARW (2023)
Kazuki Sunaga, Keisuke Sugiura, Hiroki Matsutani
An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm. CoRR (2023)
Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani
A Case for Offloading Federated Learning Server on Smart NIC. CoRR (2023)
Mizuki Yasuda, Keisuke Sugiura, Ryuto Kojima, Hiroki Matsutani
An Edge-Server Partitioning Method for 3D LiDAR SLAM on FPGAs. IPDPS Workshops (2023)
Kazuki Sunaga, Masaaki Kondo, Hiroki Matsutani
Addressing the Gap Between Training Data and Deployed Environment by On-Device Learning. IEEE Micro 43 (6) (2023)
Kenji Nemoto, Hiroki Matsutani
A Lightweight Reinforcement Learning Based Packet Routing Method Using Online Sequential Learning. IEICE Trans. Inf. Syst. 106 (11) (2023)
Takeya Yamada, Hiroki Matsutani
A Lightweight Concept Drift Detection Method for On-Device Learning on Resource-Limited Edge Devices. IPDPS Workshops (2023)
Keisuke Sugiura, Hiroki Matsutani
An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs. PDP (2023)
Keisuke Sugiura, Hiroki Matsutani
An Integrated FPGA Accelerator for Deep Learning-based 2D/3D Path Planning. CoRR (2023)
Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
Designing low-diameter interconnection networks with multi-ported host-switch graphs. Concurr. Comput. Pract. Exp. 35 (11) (2023)
Ikumi Okubo, Keisuke Sugiura, Hiroki Kawakami, Hiroki Matsutani
A Lightweight Transformer Model using Neural ODE for FPGAs. IPDPS Workshops (2023)
Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani
A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs. IEICE Trans. Inf. Syst. 106 (7) (2023)
Keisuke Sugiura, Hiroki Matsutani
P3Net: PointNet-based Path Planning on FPGA. FPT (2022)
Man Wu, Hiroki Matsutani, Masaaki Kondo
ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC. HPCC/DSS/SmartCity/DependSys (2022)
Keisuke Sugiura, Hiroki Matsutani
A Universal LiDAR SLAM Accelerator System on Low-Cost FPGA. IEEE Access 10 (2022)
Mineto Tsukada, Hiroki Matsutani
An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani
Communication Size Reduction of Federated Learning based on Neural ODE Model. CoRR (2022)
Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani
Communication Size Reduction of Federated Learning based on Neural ODE Model. CANDARW (2022)
Takeya Yamada, Hiroki Matsutani
A Sequential Concept Drift Detection Method for On-Device Learning on Low-End Edge Devices. CoRR (2022)
Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani
dsODENet: Neural ODE and Depthwise Separable Convolution for Domain Adaptation on FPGAs. PDP (2022)
Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems 90 (2022)
Hiroki Matsutani, Mineto Tsukada, Masaaki Kondo
On-Device Learning: A Neural Network Based Field-Trainable Edge AI. CoRR (2022)
Masaki Furukawa, Hiroki Matsutani
Accelerating Distributed Deep Reinforcement Learning by In-Network Experience Sampling. PDP (2022)
Keisuke Sugiura, Hiroki Matsutani
An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs. CoRR (2022)
Kenji Nemoto, Hiroki Matsutani
A Packet Routing using Lightweight Reinforcement Learning Based on Online Sequential Learning. CANDARW (2022)
Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR (2022)
Masaki Furukawa, Hiroki Matsutani
A DPDK-Based Acceleration Method for Experience Sampling of Distributed Reinforcement Learning. CoRR (2021)
Takuya Sakuma, Hiroki Matsutani
An Area-Efficient Recurrent Neural Network Core for Unsupervised Time-Series Anomaly Detection. IEICE Trans. Electron. (6) (2021)
Rei Ito, Mineto Tsukada, Hiroki Matsutani
An On-Device Federated Learning Approach for Cooperative Model Update Between Edge Devices. IEEE Access 9 (2021)
Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT (2021)
Hirohisa Watanabe, Hiroki Matsutani
Accelerating ODE-Based Neural Networks on Low-Cost FPGAs. IPDPS Workshops (2021)
Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani
A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs. CoRR (2021)
Keisuke Sugiura, Hiroki Matsutani
Particle Filter-based vs. Graph-based: SLAM Acceleration on Low-end FPGAs. CoRR (2021)
Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP (2021)
Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani
An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning. IPDPS Workshops (2021)
Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. IEICE Trans. Inf. Syst. (12) (2021)
Keisuke Sugiura, Hiroki Matsutani
An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm. IEICE Trans. Inf. Syst. (6) (2021)
Keisuke Sugiura, Hiroki Matsutani
A unified accelerator design for LiDAR SLAM algorithms for low-end FPGAs. FPT (2021)
Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani
An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning. Int. J. Netw. Comput. 11 (2) (2021)
Mineto Tsukada, Hiroki Matsutani
An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit. CoRR (2021)
Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. PDP (2020)
Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. CANDAR (Workshops) (2020)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. (12) (2020)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. (1) (2020)
Yang Qin, Hiroki Matsutani, Masaaki Kondo
A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection. iThings/GreenCom/CPSCom/SmartData/Cybermatics (2020)
Shin Morishima, Hiroki Matsutani
In-GPU Cache for Acceleration of Anomaly Detection in Blockchain. IEICE Trans. Inf. Syst. (8) (2020)
Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani
A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices. IEEE Trans. Computers 69 (7) (2020)
Takuya Sakuma, Hiroki Matsutani
An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection. COOL CHIPS (2020)
Rei Ito, Mineto Tsukada, Hiroki Matsutani
An On-Device Federated Learning Approach for Cooperative Anomaly Detection. CoRR (2020)
Keisuke Sugiura, Hiroki Matsutani
An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm. CoRR (2020)
Tokio Kibata, Mineto Tsukada, Hiroki Matsutani
An Edge Attribute-Wise Partitioning and Distributed Processing of R-GCN Using GPUs. Euro-Par Workshops (2020)
Hirohisa Watanabe, Hiroki Matsutani
Accelerating ODE-Based Neural Networks on Low-Cost FPGAs. CoRR (2020)
Hiroki Oikawa, Tomoya Nishida, Ryuichi Sakamoto, Hiroki Matsutani, Masaaki Kondo
Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine. ITSC (2020)
Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani
An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning. CANDAR (2020)
Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani
An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning. CoRR (2020)
Tomoya Itsubo, Mineto Tsukada, Hiroki Matsutani
Performance and Cost Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core. COOL CHIPS (2019)
Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano
Key-value Store Chip Design for Low Power Consumption. COOL CHIPS (2019)
Takuma Iwata, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani
An FPGA-Based Change-Point Detection for 10Gbps Packet Stream. IEICE Trans. Inf. Syst. (12) (2019)
Rei Ito, Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani
An Adaptive Abnormal Behavior Detection using Online Sequential Learning. CSE/EUC (2019)
Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
Designing High-Performance Interconnection Networks with Host-Switch Graphs. IEEE Trans. Parallel Distributed Syst. 30 (2) (2019)
Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani
A Neural Network Based On-device Learning Anomaly Detector for Edge Devices. CoRR (2019)
Ryuta Kawano, Hiroki Matsutani, Hideharu Amano
Deadlock-Free Layered Routing for Infiniband Networks. CANDAR Workshops (2019)
Michihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova
Sparse 3-D NoCs with Inductive Coupling. DAC (2019)
Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. CANDAR Workshops (2018)
Shin Morishima, Hiroki Matsutani
Accelerating Blockchain Search of Full Nodes Using GPUs. PDP (2018)
Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman
LaKe: An Energy Efficient, Low Latency, Accelerated Key-Value Store. CoRR (2018)
Koya Mitsuzuka, Yuta Tokusashi, Hiroki Matsutani
MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories. FPT (2018)
Shin Morishima, Hiroki Matsutani
Acceleration of Anomaly Detection in Blockchain Using In-GPU Cache. ISPA/IUCC/BDCloud/SocialCom/SustainCom (2018)
Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani
OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector. Euro-Par Workshops (2018)
Truong Thao Nguyen, Hiroki Matsutani, Michihiro Koibuchi
Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications. NCA (2018)
Yuma Sakakibara, Shin Morishima, Kohei Nakamura, Hiroki Matsutani
A Hardware-Based Caching System on FPGA NIC for Blockchain. IEICE Trans. Inf. Syst. (5) (2018)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano
k-Optimized Path Routing for High-Throughput Data Center Networks. CANDAR (2018)
Kaho Okuyama, Yuta Tokusashi, Takuma Iwata, Mineto Tsukada, Kazumasa Kishiki, Hiroki Matsutani
Network Optimizations on Prediction Server with Multiple Predictors. ISPA/IUCC/BDCloud/SocialCom/SustainCom (2018)
Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman
LaKe: The Power of In-Network Computing. ReConFig (2018)
Yuma Sakakibara, Yuta Tokusashi, Shin Morishima, Hiroki Matsutani
Accelerating Blockchain Transfer System Using FPGA-Based NIC. ISPA/IUCC/BDCloud/SocialCom/SustainCom (2018)
Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. MCSoC (2018)
Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano
Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Int. J. Netw. Comput. 8 (1) (2018)
Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. NOCS (2018)
Takuma Iwata, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani
Accelerating Online Change-Point Detection Algorithm Using 10 GbE FPGA NIC. Euro-Par Workshops (2018)
Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. IEICE Trans. Inf. Syst. (9) (2018)
Terrence S. T. Mak, Hiroki Matsutani, Partha Pratim Pande
Special session on bringing cores closer together: The wireless revolution in on-chip communication. VTS (2018)
Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova
A Case for Uni-directional Network Topologies in Large-Scale Clusters. CLUSTER (2017)
Yao Hu, Hiroaki Hara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
Towards Tightly-coupled Datacenter with Free-space Optical Links. ICCBDC (2017)
Ami Hayashi, Hiroki Matsutani
An FPGA-based In-NIC Cache Approach for Lazy Learning Outlier Filtering. PDP (2017)
Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
In-switch approximate processing: Delayed tasks management for MapReduce applications. FPL (2017)
Yuma Sakakibara, Kohei Nakamura, Hiroki Matsutani
An FPGA NIC Based Hardware Caching for Blockchain. HEART (2017)
Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki
Building block multi-chip systems using inductive coupling through chip interface. ISOCC (2017)
Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. ICPADS (2017)
Yuta Tokusashi, Hiroki Matsutani
Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches. IEEE Micro 37 (5) (2017)
Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. IEICE Trans. Inf. Syst. (8) (2017)
Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers 66 (4) (2017)
Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. ICPP (2017)

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Publication Activity (10 Years)

Top Topics

Top Venues

Hiroki Matsutani