Tadao Nakamura

Publication Activity (10 Years)

Years Active: 1981-2023
Publications (10 Years): 8

Top Topics

Nonparametric Regression

Message Transmission

Top Venues

Quantum Inf. Process.

Publications

Koji Nagata, Do Ngoc Diep, Tadao Nakamura
Two symmetric measurements may cause an unforeseen effect. Quantum Inf. Process. 22 (2) (2023)
Koji Nagata, Do Ngoc Diep, Tadao Nakamura
Computational complexity in high-dimensional quantum computing. Quantum Mach. Intell. 4 (2) (2022)
Koji Nagata, Renata Wong, Do Ngoc Diep, Tadao Nakamura
Quantum cryptography based on an algorithm for determining simultaneously all the mappings of a Boolean function. IACR Cryptol. ePrint Arch. 2021 (2021)
Do Ngoc Diep, Koji Nagata, Tadao Nakamura
Nonparametric Regression Quantum Neural Networks. CoRR (2020)
Tadao Nakamura
An Introduction to Marching Memory (MM). 3DIC (2019)
Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash
Panel discussions: "Cool chips for the next decade". COOL Chips (2017)
Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers 66 (4) (2017)
Tadao Nakamura
Message from the advisory committee chair. COOL Chips (2016)
Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. NOCS (2015)
Yukinori Sato, Yasushi Inoguchi, Tadao Nakamura
Identifying Program Loop Nesting Structures during Execution of Machine Code. IEICE Trans. Inf. Syst. (9) (2014)
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
Design of a low power NoC router using Marching Memory Through type. NOCS (2014)
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
A low power NoC router using the marching memory through type. COOL Chips (2014)
Tadao Nakamura
Message from the advisory committee chair. COOL Chips (2014)
Tadao Nakamura, Yoriko Mizushima, Hideki Kitada, Young-Suk Kim, Nobuhide Maeda, Shoichi Kodama, Ryuichi Sugie, Hiroshi Hashimoto, Akihito Kawai, Kazuhisa Arai, Akira Uedono, Takayuki Ohba
Influence of wafer thinning process on backside damage in 3D integration. 3DIC (2013)
Koji Nagata, Tadao Nakamura
An additional condition for Bell experiments for accepting local realistic theories. Quantum Inf. Process. 12 (12) (2013)
Tadao Nakamura
Message from the Advisory Committee Chair. COOL Chips (2013)
Yukinori Sato, Yasushi Inoguchi, Tadao Nakamura
Whole program data dependence profiling to unveil parallel regions in the dynamic execution. IISWC (2012)
Yukinori Sato, Yasushi Inoguchi, Wayne Luk, Tadao Nakamura
Evaluating reconfigurable dataflow computing using the Himeno benchmark. ReConFig (2012)
Nobuhide Maeda, Young-Suk Kim, Y. Hikosaka, T. Eshita, Hideki Kitada, K. Fujimoto, Yoriko Mizushima, K. Suzuki, Tadao Nakamura, Akihito Kawai, Kazuhisa Arai, Takayuki Ohba
Development of ultra-thinning technology for logic and memory heterogeneous stack applications. 3DIC (2011)
Yukinori Sato, Yasushi Inoguchi, Tadao Nakamura
On-the-fly detection of precise loop nests across procedures on a dynamic binary translation system. Conf. Computing Frontiers (2011)
K. Suzuki, Tadao Nakamura
Development of a peristaltic pump based on bowel peristalsis using for artificial rubber muscle. IROS (2010)
Hideharu Amano, Tadao Nakamura
Guest Editors' Introduction: ICFPT 2007. ACM Trans. Reconfigurable Technol. Syst. 2 (2) (2009)
Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura
Power Estimation of Partitioned Register Files in a Clustered Architecture with Performance Evaluation. IEICE Trans. Inf. Syst. (3) (2007)
Yoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu, Ken-ichi Suzuki, Tadao Nakamura, Nobuyuki Ohba
Ray Tracing Hardware System Using Plane-Sphere Intersections. FPL (2006)
Takeshi Miura, Kentaro Sano, Ken-ichi Suzuki, Tadao Nakamura
A Competitive Learning Algorithm with Controlling Maximum Distortion. J. Adv. Comput. Intell. Intell. Informatics 9 (2) (2005)
Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura
An Operand Status Based Instruction Steering Scheme for Clustered Architectures. CDES (2005)
Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura
Cooperation of Neighboring PEs in Clustered Architectures. SBAC-PAD (2005)
Kentaro Sano, Yusuke Kobayashi, Tadao Nakamura
Differential coding scheme for efficient parallel image composition on a PC cluster system. Parallel Comput. 30 (2) (2004)
Kentaro Sano, Shintaro Momose, Hiroyuki Takizawa, Hiroaki Kobayashi, Tadao Nakamura
Efficient parallel processing of competitive learning algorithms. Parallel Comput. 30 (12) (2004)
Shintaro Momose, Kentaro Sano, K. Suzuki, Tadao Nakamura
Parallel competitive learning algorithm for fast codebook design on partitioned space. CLUSTER (2004)
Kentaro Sano, Chiaki Takagi, Ryusuke Egawa, Ken-ichi Suzuki, Tadao Nakamura
A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm. ITCC (1) (2004)
Tadao Nakamura
Toward Architecting and Designing Novel Computers. Asia-Pacific Computer Systems Architecture Conference (2003)
C. D. Lima, Kentaro Sano, Tadao Nakamura
Hardware Support for Concurrent Execution of Loops Containing Loop-carried Data Dependences. IASTED PDCS (2002)
Tomoyuki Nagase, Takashi Araki, Yoshio Yoshioka, Tadao Nakamura
Moderating traffic flow over conventional ATM service. ISCC (2002)
Clecio Donizete Lima, Tadao Nakamura
Exploiting Loop-Level Parallelism with the Shift Architecture. SBAC-PAD (2002)
Kentaro Sano, Shintaro Momose, Hiroyuki Takizawa, Taira Nakajima, C. D. Lima, Hiroaki Kobayashi, Tadao Nakamura
Parallel Algorithm for the Law-of-the-Jungle Learning to the Fast Design of Optimal Codebooks. IASTED PDCS (2002)
Hiroaki Kobayashi, Ken-ichi Suzuki, Kentaro Sano, Yoshiyuki Kaeriyama, Yasumasa Saida, Nobuyuki Oba, Tadao Nakamura
3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis. ICCD (2001)
Emad Rashid, Takashi Araki, Tadao Nakamura
An Active Network for Improving Performance of Traffic Flow over Conventional ATM Service. ICN (2) (2001)
Emad Rashid, Yoshio Yoshioka, Takashi Araki, Tadao Nakamura
Variable-Length Coding based on Bent Sequences for W.ireless Advertising. ISCC (2001)
Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura
Scaling Up Of Wave Pipelines. VLSI Design (2001)
Lei Li, Tadao Nakamura
Fast parallel algorithms for vandermonde determinants. Int. J. Comput. Math. 73 (4) (2000)
Tadao Nakamura
Cool Chips III. IEEE Micro 20 (6) (2000)
Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura
Reconfigurable synchronized dataflow processor. ASP-DAC (2000)
Ken-ichi Suzuki, Nobuyuki Oba, Shigenori Shimizu, Hiroaki Kobayashi, Tadao Nakamura
Time stamp invalidation of TLB-unified cache and its performance evaluation. Systems and Computers in Japan 30 (11) (1999)
Taira Nakajima, Hiroyuki Takizawa, Hiroaki Kobayashi, Tadao Nakamura
A self-organizing network system forming memory from nonstationary probability distributions. IJCNN (1999)
Tadao Nakamura
Introducing cool chips. IEEE Micro 19 (4) (1999)
Takuya Nakaike, Takehito Sasaki, Masayuki Katahira, Hiroaki Kobayashi, Tadao Nakamura
A scheduling method for instruction-level parallel processing of vectorand scalar instructions. Systems and Computers in Japan 30 (13) (1999)
Kouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura
Automated Design of Wave Pipelined Multiport Register Files. ASP-DAC (1998)
Jie Hu, Tadao Nakamura, Lei Li
Convergence, Complexity and Simulation of Monotone Asynchronous Iterative Method for Computing Fixed Point on a Distributed Computer. Parallel Algorithms Appl. 11 (1-2) (1997)
Masafumi Takahashi, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura
Decoupled modified-bit cache. Systems and Computers in Japan 28 (6) (1997)
Jie Hu, Tadao Nakamura, Lei Li
Asynchronous Monotone Newton Iterative Method on Distributed Computers. Parallel Algorithms Appl. 12 (4) (1997)
Kentaro Sano, Hiroyuki Kitajima, Hiroaki Kobayashi, Tadao Nakamura
Parallel processing of the shear-warp factorization with the binary-swap method on a distributed-memory multiprocessor system. PRS (1997)
Masaaki Nishi, Junji Furuya, Tadao Nakamura
A construction of back-propagation neural networks including time delay elements (BPD). Systems and Computers in Japan 27 (10) (1996)
Hiroaki Kobayashi, Hitoshi Yamauchi, Yuichiro Toh, Tadao Nakamura
A Hierarchical Parallel Processing System for the Multipass-Rendering Method. IPPS (1996)
Lei Li, Jie Hu, Tadao Nakamura
A Simple Parallel Algorithm for Polynomial Evaluation. SIAM J. Sci. Comput. 17 (1) (1996)
Lei Li, Tadao Nakamura
The Convergence of Asynchronous Iterations for the Fixed Point of a Splitting Operator. Parallel Algorithms Appl. 7 (3-4) (1995)
Jie Hu, Lei Li, Tadao Nakamura
A Divide-and-inner Product Parallel Algorithm for Polynomial Evaluation. Parallel Algorithms Appl. 6 (1) (1995)
Jie Hu, Tadao Nakamura, Lei Li
The Convergence of Asynchronous Monotone Newton Iterations on Distributed Computer. PPSC (1995)
Masayuki Katahira, Takehito Sasaki, Hong Shen, Hiroaki Kobayashi, Tadao Nakamura
Software pipelining for Jetpipeline architecture. ISPAN (1994)
Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura
An Adaptive Network Routing Method by Electrical-Circuit Modeling. INFOCOM (1993)
Masa-Aki Fukase, Tadao Nakamura
Parallel Processing and Hardware Support of Symbols. ICTAI (1993)
Masa-Aki Fukase, Tadao Nakamura
Semiparallel execution of compiled Lisp programs. COMPSAC (1991)
Hiroaki Kobayashi, Satoshi Nishimura, Hideyuki Kubota, Tadao Nakamura, Yoshiharu Shigei
Load balancing strategies for a parallel ray-tracing system based on constant subdivision. Vis. Comput. 4 (4) (1988)
Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, Takahiko Murayama, Yoshio Yoshioka
Realization of computers using programmable logic units. Systems and Computers in Japan 18 (8) (1987)
Hiroaki Kobayashi, Tadao Nakamura, Yoshiharu Shigei
Parallel processing of an object space for image synthesis using ray tracing. Vis. Comput. 3 (1) (1987)
Takahiko Murayama, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, Yoshio Yoshioka
Characteristics of a programmable logic unit. Systems and Computers in Japan 18 (9) (1987)
Nobuyuki Oba, Tadao Nakamura, Yoshiharu Shigei
An adaptive routing method for computer networks by electric-circuit modeling. Systems and Computers in Japan 18 (3) (1987)
Takahiko Murayama, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, Yoshio Yoshioka
Performance evaluation of a computer using programmable logic units. Systems and Computers in Japan 18 (8) (1987)
Nobuyuki Oba, Tadao Nakamura, Yoshiharu Shigei
Signal processing on a parallel pipeline-structured data-flow computer system. Systems and Computers in Japan 17 (4) (1986)
Jun Miyajima, Noboru Endo, Tadao Nakamura, Yoshiharu Shigei
Matrix representation of programs within an intelligent link. Systems and Computers in Japan 17 (1) (1986)
Noboru Endo, Tadao Nakamura, Yoshiharu Shigei
A Hierarchical General-Purpose Pipeline System. Systems and Computers in Japan 17 (4) (1986)
Masayuki Tomisawa, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei
Evaluating the parallelism of the feed-forward machine and algorithms of the machine. Systems and Computers in Japan 16 (4) (1985)
Tadao Nakamura, Hiroaki Kobayashi, Jun Miyajima, Noboru Endo, Yoshiharu Shigei
A Language Processor of an Intelligent Link System. ICC (2) (1984)
Kuninobu Tanno, Tadao Nakamura, Risaburo Sato
An Analysis of the Receiving Behaviour of a Window Flow Control Mechanism in Packet Switching Networks. ICC (3) (1984)
Makoto Hasegawa, Tadao Nakamura, Yoshiharu Shigei
Distributed Communicating Media-A Multitrack Bus-Capable of Concurrent Data Exchanging. ISCA (1981)