Yasunobu Nakase

Publication Activity (10 Years)

Years Active: 1993-2014
Publications (10 Years): 0

Top Topics

Computer Controlled

Permanent Magnet

Functional Verification

Top Venues

IEICE Trans. Electron.

IEEE J. Solid State Circuits

Publications

Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
Design of a low power NoC router using Marching Memory Through type. NOCS (2014)
Ryota Yasudo, Takahiro Kagami, Hideharu Amano, Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu, Tadao Nakamura
A low power NoC router using the marching memory through type. COOL Chips (2014)
Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu
On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration. IEEE J. Solid State Circuits 48 (8) (2013)
Yasunobu Nakase, Yasuhiro Ido, Tsukasa Oishi, Toru Shimizu
On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes. IEICE Trans. Electron. (11) (2013)
Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu
on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration. CICC (2012)
Yasunobu Nakase, Shinichi Hirose, Toru Goda, Kehui Hu, Hiroshi Onoda, Yasuhiro Ido, Hiroyuki Kondo, Wei Kong, Wei Zhang, Tsukasa Oishi, Shintaro Mori, Toru Shimizu
0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers. A-SSCC (2011)
Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba
A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. IEEE J. Solid State Circuits 36 (2) (2001)
Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34 (4) (1999)
Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits 32 (2) (1997)
Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko
Authors Reply. IEEE J. Solid State Circuits 32 (2) (1997)
Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits 31 (4) (1996)
Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits 31 (6) (1996)
Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits 31 (8) (1996)
Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko
A BiCMOS wired-OR logic. IEEE J. Solid State Circuits 30 (6) (1995)
Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara
A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. ICCD (1993)