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A 286 MHz 64-b floating point multiplier with enhanced CG operation.
Hiroshi Makino
Hiroaki Suzuki
Hiroyuki Morinaka
Yasunobu Nakase
Koichiro Mashiko
Tadashi Sumi
Published in:
IEEE J. Solid State Circuits (1996)
Keyphrases
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floating point
fixed point
square root
instruction set
floating point arithmetic
high speed
sparse matrices
image processing
reinforcement learning
high resolution
scheduling problem
higher order
constraint satisfaction problems
interval arithmetic