Koichiro Mashiko

Publication Activity (10 Years)

Years Active: 1985-2019
Publications (10 Years): 1

Top Topics

Intrusion Detection

Power Consumption

Security Problems

Top Venues

Publications

Pyi Phyo Aung, Koichiro Mashiko, Nordinah Binti Ismail, Chia Yee Ooi
Evaluation of SRAM PUF Characteristics and Generation of Stable Bits for IoT Security. IRICT (2019)
Hao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada
A Second-Order Multibit Complex Bandpass DeltaSigmaAD Modulator with I, Q Dynamic Matching and DWA Algorithm. IEICE Trans. Electron. (6) (2007)
Hao San, Akira Hayakawa, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Kazuyuki Kobayashi, Haruo Kobayashi, Tatsuji Matsuura, Kouichi Yahagi, Junya Kudoh, Hideo Nakane, Masao Hotta, Toshiro Tsukada, Koichiro Mashiko, Atsushi Wada
Complex Bandpass DeltaSigmaAD Modulator Architecture without I, Q-Path Crossing Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Masafumi Uemori, Haruo Kobayashi, Tomonari Ichikawa, Atsushi Wada, Koichiro Mashiko, Toshiro Tsukada, Masao Hotta
High-Speed Continuous-Time Subsampling Bandpass DeltaSigmaAD Modulator Architecture Employing Radio Frequency DAC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Toru Nakura, Kimio Ueda, Kazuo Kubo, Yoshio Matsuda, Koichiro Mashiko, Tsutomu Yoshihara
A 3.6-Gb/s 340-mW 16: 1 pipe-lined multiplexer using 0.18 μm SOI-CMOS technology. IEEE J. Solid State Circuits 35 (5) (2000)
Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits 32 (2) (1997)
Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko
Authors Reply. IEEE J. Solid State Circuits 32 (2) (1997)
Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano
A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. ICCD (1997)
Kiniio Ueda, Hiroaki Suzuki, Kakutaro Suda, Hirofumi Shinohara, Koichiro Mashiko
A 64-bit carry look ahead adder using pass transistor BiCMOS gates. IEEE J. Solid State Circuits 31 (6) (1996)
Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Koichiro Mashiko
A fully compensated active pull-down ECL circuit with self-adjusting driving capability. IEEE J. Solid State Circuits 31 (1) (1996)
Koichiro Mashiko
How to design low-power digital cellular phones. ISLPED (1996)
Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits 31 (4) (1996)
Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits 31 (6) (1996)
Hisayasu Sato, Kenichi Kashiwagi, Kazuhito Niwano, Tetsuya Iga, Tatsuhiko Ikeda, Koichiro Mashiko, Tadashi Sumi, Koji Tsuchihashi
A 1.9-GHz single chip IF transceiver for digital cordless phones. IEEE J. Solid State Circuits 31 (12) (1996)
Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits 31 (8) (1996)
Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko
A BiCMOS wired-OR logic. IEEE J. Solid State Circuits 30 (6) (1995)
Hisayasu Sato, Kimio Ueda, Nagisa Sasaki, Tatsuhiko Ikeda, Koichiro Mashiko
A voltage compensated series-gate bipolar circuit operating at sub-2 V. IEEE J. Solid State Circuits 29 (10) (1994)
Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano
Test Pattern Considerations for Fault Tolerant High Density DRAM. ITC (1985)