Hiroshi Makino

Publication Activity (10 Years)

Years Active: 1980-2016
Publications (10 Years): 3

Top Topics

Motion Estimation Algorithm

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Masahiro Hiramori, Ryota Bandou, Shuhei Iwade, Hiroshi Makino, Tsutomu Yoshimura, Yoshio Matsuda
A study on fast motion estimation algorithm. GCCE (2016)
Ryota Bnadou, Masahiro Hiramori, Shuhei Iwade, Hiroshi Makino, Tutomu Yoshimura, Yoshio Matsuda
A study on motion estimation algorithm for moving pictures. GCCE (2016)
Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto
A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2016)
Hiroshi Makino, Shunsuke Kamijo
The Challenge of Collaboration among Academies and Asia Pacific for ITS R&D. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2015)
Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2014)
Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda
The LSI implementation of a memory based field programmable device for MCU peripherals. DDECS (2014)
Shunji Nakata, Hiroshi Makino, Yoshio Matsuda
A new stepwise adiabatic charging circuit with a smaller capacitance in a regenerator than a load capacitance. MWSCAS (2014)
Shunji Nakata, Hiroki Hanazono, Hiroshi Makino, Hiroki Morimura, Masayuki Miyama, Yoshio Matsuda
Increase in Read Noise Margin of Single-Bit-Line SRAM Using Adiabatic Change of Word Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. 22 (3) (2014)
Hiroshi Makino
Development of the SCARA. J. Robotics Mechatronics 26 (1) (2014)
Shunji Nakata, Hiroshi Makino, Ryota Honda, Masayuki Miyama, Yoshio Matsuda
Analysis of voltage, Current and Energy dissipation of Stepwise Adiabatic Charging of a capacitor using a nonresonant inductor Current. J. Circuits Syst. Comput. 23 (3) (2014)
Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda
Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2013)
Shunji Nakata, Ryota Honda, Hiroshi Makino, Shin'ichiro Mutoh, Masayuki Miyama, Yoshio Matsuda
General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2012)
Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. 6 (4) (2012)
Shunji Nakata, Ryota Honda, Hiroshi Makino, Hiroki Morimura, Yoshio Matsuda
Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current. MWSCAS (2012)
Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Shunji Nakata, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda
Stable adiabatic circuit using advanced series capacitors and time variation of energy dissipation. IEICE Electron. Express 7 (9) (2010)
Shunji Nakata, Hirotsugu Suzuki, Ryota Honda, Takahito Kusumoto, Shin'ichiro Mutoh, Hiroshi Makino, Masayuki Miyama, Yoshio Matsuda
Adiabatic SRAM with a shared access port using a controlled ground line and step-voltage circuit. ISCAS (2010)
Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara
Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access. IEEE J. Solid State Circuits 44 (3) (2009)
Masako Fujii, Koji Nii, Hiroshi Makino, Shigeki Ohbayashi, Motoshige Igarashi, Takeshi Kawamura, Miho Yokota, Nobuhiro Tsuda, Tomoaki Yoshizawa, Toshikazu Tsutsui, Naohiko Takeshita, Naofumi Murata, Tomohiro Tanaka, Takanari Fujiwara, Kyoko Asahina, Masakazu Okada, Kazuo Tomita, Masahiko Takeuchi, Shigehisa Yamamoto, Hiromitsu Sugimoto, Hirofumi Shinohara
A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology. IEICE Trans. Electron. (8) (2008)
Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. IEEE J. Solid State Circuits 43 (4) (2008)
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die. IEEE J. Solid State Circuits 43 (1) (2008)
Hiroaki Suzuki, Masanori Kurimoto, Tadao Yamanaka, Hidehiro Takata, Hiroshi Makino, Hirofumi Shinohara
Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. ISLPED (2008)
Masako Fujii, Hiroaki Suzuki, Hiromi Notani, Hiroshi Makino, Hirofumi Shinohara
On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect. ESSCIRC (2008)
Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations. IEEE J. Solid State Circuits 43 (1) (2008)
Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. ISSCC (2007)
Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura, Rei Akiyama, Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata, Makoto Nagata
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs. ISSCC (2007)
Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE J. Solid State Circuits 42 (4) (2007)
Hiroshi Makino, Akitaka Kato, Yasunori Yamazaki
Research and Commercialization of SCARA Robot -The Case of Industry-University Joint Research and Development-. Int. J. Autom. Technol. 1 (1) (2007)
Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. ISSCC (2007)
Yasumasa Tsukamoto, Koji Nii, Susumu Imaoka, Yuji Oda, Shigeki Ohbayashi, Tomoaki Yoshizawa, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara
Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability. ICCAD (2005)
Niichi Itoh, Yasumasa Tsukamoto, Takeshi Shibagaki, Koji Nii, Hidehiro Takata, Hiroshi Makino
A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure. ISCAS (1) (2005)
Koji Nii, Yasumasa Tsukamoto, Tomoaki Yoshizawa, Susumu Imaoka, Yoshinobu Yamagami, Toshikazu Suzuki, Akinori Shibayama, Hiroshi Makino, Shuhei Iwade
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications. IEEE J. Solid State Circuits 39 (4) (2004)
Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, Yasutaka Horiba
A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree. IEEE J. Solid State Circuits 36 (2) (2001)
Noriaki Kiyohiro, Hiroshi Makino, Hideo Mori
Robot contest "Robocon Yamanashi". J. Robotics Mechatronics 10 (1) (1998)
Koji Nii, Hiroshi Makino, Yoshiki Tsujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano
A low power SRAM using auto-backgate-controlled MT-CMOS. ISLPED (1998)
Vojin G. Oklobdzija, Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. IEEE J. Solid State Circuits 32 (2) (1997)
Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko
Authors Reply. IEEE J. Solid State Circuits 32 (2) (1997)
Hiroaki Suzuki, Hiroshi Makino, Koichiro Mashiko, Hisanori Hamano
A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme. ICCD (1997)
Hiroshi Makino, Hiroaki Suzuki, Hiroyuki Morinaka, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
A 286 MHz 64-b floating point multiplier with enhanced CG operation. IEEE J. Solid State Circuits 31 (4) (1996)
Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka, Hirofumi Shinohara, Koichiro Mashiko
An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture. IEEE J. Solid State Circuits 31 (6) (1996)
Hiroaki Suzuki, Hiroyuki Morinaka, Hiroshi Makino, Yasunobu Nakase, Koichiro Mashiko, Tadashi Sumi
Leading-zero anticipatory logic for high-speed floating point addition. IEEE J. Solid State Circuits 31 (8) (1996)
Yasunobu Nakase, Hiroaki Suzuki, Hiroshi Makino, Hirofumi Shinohara, Koichiro Mashiko
A BiCMOS wired-OR logic. IEEE J. Solid State Circuits 30 (6) (1995)
Hiroshi Makino, Yasunobu Nakase, Hirofumi Shinohara
A 8.8-ns 54 54-Bit Multiplier Using New Redundant Binary Architecture. ICCD (1993)
Hiroshi Makino
Development of the Spherical SCARA Robot. J. Robotics Mechatronics 1 (3) (1989)
Hiroshi Makino
Beta: An Automatic Kana-Kanji Translation System. Computer 18 (1) (1985)
Hiroshi Makino, Makoto Kizawa
An Automatic Translation System Of Non-Segmented Kana Sentences Into Kanji-Kana Sentences. COLING (1980)