Tsutomu Yoshimura

Publication Activity (10 Years)

Years Active: 1996-2023
Publications (10 Years): 16

Top Topics

Applied Sciences

Cmos Technology

Energy Efficient

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Ryuji Komabayashi, Tsutomu Yoshimura
Analysis of the Electromagnetic Coupling of Two Phase-Locked Loops. ISCAS (2023)
Tsutomu Yoshimura
Self-Coupling and Mutual Pulling in Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (8) (2022)
Tsutomu Yoshimura
Study of Injection Pulling of Oscillators in Phase-Locked Loops. IEEE Trans. Very Large Scale Integr. Syst. 29 (2) (2021)
Tsutomu Yoshimura
Mitigation of Mutual Pulling in Two Phase-locked Loops. NEWCAS (2021)
Takao Kihara, Tomoya Takahashi, Tsutomu Yoshimura
Digital Mismatch Correction for Bandpass Sampling Four-Channel Time-Interleaved ADCs in Direct-RF Sampling Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2019)
Takao Kihara, Keisuke Miyakoshi, Tsutomu Yoshimura
Digital Third-Order Nonlinearity Correction for Time-Interleaved A/D Converters with VCOs. ISCAS (2019)
Fukuyama Tokuya, Takao Kihara, Tsunehiro Yoshio, Tsutomu Yoshimura
A Standard-cell Based A/D Converter with a Back-gate VCO and a Fat Tree Encoder. APCCAS (2018)
Yuma Isobe, Takao Kihara, Tsutomu Yoshimura
A Polyphase Decimation Filter for Time-Interleaved ADCs in Direct-RF Sampling Receivers. APCCAS (2018)
Hiroyuki Kobayashi, Kazuo Kumamoto, Tsutomu Yoshimura, Toshio Haga, Muneyoshi Iyota, Makoto Katoh
A Design of Engineering PBL on Embedded System for Novice Freshmen Students. TENCON (2018)
Kazuki Miyao, Tatsuya Okafuji, Takao Kihara, Tsutomu Yoshimura
Study of mutual injection pulling in a 5-GHz, 0.18-μm CMOS cascaded PLL. APCCAS (2018)
Tomoya Takahashi, Takao Kihara, Tsutomu Yoshimura
Digital correction of mismatches in time-interleaved ADCs for digital-RF receivers. ICECS (2017)
Mayu Kobayashi, Yuya Masui, Takao Kihara, Tsutomu Yoshimura
Spur reduction by self-injection loop in a fractional-N PLL. ICECS (2017)
Takao Kihara, Hiroyuki Yano, Tsutomu Yoshimura
Design of cascaded integrator-comb decimation filters for direct-RF sampling receivers. ISCAS (2017)
Naohiro Fujii, Shuei Morishita, Takao Kihara, Tsutomu Yoshimura
A 2.6GHz subharmonically injection-locked PLL with low-spur and wide-lock-range injection. NEWCAS (2016)
Takao Kihara, Shigesato Matsuda, Tsutomu Yoshimura
Analysis and design of differential LNAs with on-chip transformers in 65-nm CMOS technology. NEWCAS (2016)
Masahiro Hiramori, Ryota Bandou, Shuhei Iwade, Hiroshi Makino, Tsutomu Yoshimura, Yoshio Matsuda
A study on fast motion estimation algorithm. GCCE (2016)
Shuei Morishita, Shinji Shimizu, Takao Kihara, Tsutomu Yoshimura
Subharmonically injection-locked PLL with variable pulse-width injections. ISCAS (2015)
Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2014)
Shinji Shimizu, Junki Mizuno, Shuei Morishita, Koichiro Hida, Tsutomu Yoshimura
Analysis and modeling of oscillators with interference noise. ICECS (2014)
Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda
Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2013)
Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. 6 (4) (2012)
Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Tsutomu Yoshimura, Atsushi Iwata
A study of interference in synchronous systems. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2006)
Tsutomu Yoshimura, Atsushi Iwata
An analysis of interference in synchronous systems. IEICE Electron. Express 1 (15) (2004)
Tsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, Masahiko Ishiwaki
A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology. CICC (2002)
Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34 (4) (1999)
Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi
A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication. IEEE J. Solid State Circuits 31 (7) (1996)