Atsushi Iwata

Publication Activity (10 Years)

Years Active: 1982-2020
Publications (10 Years): 5

Top Topics

Breast Cancer Detection

Sampling Methods

Delay Insensitive

Top Venues

IEEE Trans. Biomed. Circuits Syst.

Publications

Takamaro Kikkawa, Yoshihiro Masui, Akihiro Toya, Hiroyuki Ito, Takuichi Hirano, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Tsuyoshi Matsumaru, Michimasa Yamaguchi, Mitsutoshi Sugawara, Afreen Azhari, Hang Song, Shinsuke Sasada, Atsushi Iwata
CMOS Gaussian Monocycle Pulse Transceiver for Radar-Based Microwave Imaging. IEEE Trans. Biomed. Circuits Syst. 14 (6) (2020)
Akihiro Toya, Takamaro Kikkawa, Yoshihiro Masui, Mitsutoshi Sugawara, Hiroyuki Ito, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Toshifumi Imamura, Atsushi Iwata
Shifting Clock Jitter and Phase Interval for Impulse-Radar-Based Breast Cancer Detection. BioCAS (2019)
Yoshihiro Masui, Akihiro Toya, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa
Gaussian Monocycle Pulse Generator with Calibration Circuit for Breast Cancer Detection. BioCAS (2018)
Yoshihiro Masui, Akihiro Toya, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa
Differential equivalent time sampling receiver for breast cancer detection. BioCAS (2017)
Akihiro Toya, Yoshihiro Masui, Mitsutoshi Sugawara, Tomoaki Maeda, Masahiro Ono, Yoshitaka Murasaka, Atsushi Iwata, Takamaro Kikkawa
Investigation of phase noise and jitter in CMOS sampling clock generation circuits for time-domain breast cancer detection system. BioCAS (2017)
Kazumi Aono, Atsushi Iwata, Hideki Takase, Kazuyoshi Takagi, Naofumi Takagi
An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality. HPCC/CSS/ICESS (2014)
Kazuhiro Shimonomura, Seiji Kameda, Atsushi Iwata, Tetsuya Yagi
Wide-Dynamic-Range APS-Based Silicon Retina With Brightness Constancy. IEEE Trans. Neural Networks 22 (9) (2011)
Atsushi Iwata, Yoshitaka Murasaka, Tomoaki Maeda, Takafumi Ohmoto
Background Calibration Techniques for Low-Power and High-Speed Data Conversion. IEICE Trans. Electron. (6) (2011)
Yudai Honma, Masaki Aida, Hideyuki Shimonishi, Atsushi Iwata
A New Multi-Path Routing Methodology Based on Logit-Type Probability Assignment. IEICE Trans. Commun. (8) (2011)
Takeshi Yoshida, Yoshihiro Masui, Ryoji Eki, Atsushi Iwata, Masayuki Yoshida, Kazumasa Uematsu
A Neural Recording Amplifier with Low-Frequency Noise Suppression. IEICE Trans. Electron. (6) (2010)
Kunihiko Gotoh, Hiroshi Ando, Atsushi Iwata
A 1.0-V 10-b 30-MS/s 3.4-mW rail-to-rail pipelined ADC using a new front-end MDAC. IEICE Electron. Express 6 (4) (2009)
Hideyuki Shimonishi, Hideya Ochiai, Nobuyuki Enomoto, Atsushi Iwata
Building Hierarchical Switch Network Using OpenFlow. INCoS (2009)
Takeshi Yoshida, Yoshihiro Masui, Ryoji Eki, Atsushi Iwata, Masayuki Yoshida, Kazumasa Uematsu
A Neural Signal Detection Amplifier with Low-frequency Noise Suppression. ISCAS (2009)
Yoshihiro Masui, Takeshi Yoshida, Atsushi Iwata
A 2.0 Vpp Input, 0.5 V Supply Delta Amplifier with A-to-D Conversion. IEICE Trans. Electron. (6) (2009)
Hideyuki Shimonishi, Takashi Yoshikawa, Atsushi Iwata
Off-the-path flow handling mechanism forhigh-speed and programmable traffic management. PRESTO (2008)
Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata
High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections. Hot Interconnects (2008)
Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata
High-Speed, Short-Latency Multipath Ethernet for Data Center Area Communications. GLOBECOM (2008)
Yoshihiro Masui, Takeshi Yoshida, Atsushi Iwata
Low power and low voltage chopper amplifier without LPF. IEICE Electron. Express 5 (22) (2008)
Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
Chip-Level Substrate Coupling Analysis with Reference Structures for Verification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2007)
Hideo Yoshimi, Nobuyuki Enomoto, Zhenlong Cui, Kazuo Takagi, Atsushi Iwata
NAT Traversal Technology of Reducing Load on Relaying Server for P2P Connections. CCNC (2007)
Adrian Farrel, Arun Satyanarayana, Atsushi Iwata, Norihito Fujita, Gerald R. Ash
Crankback Signaling Extensions for MPLS and GMPLS RSVP-TE. RFC 4920 (2007)
Atsushi Iwata, Takeshi Yoshida, Mamoru Sasaki
Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices. IEICE Trans. Electron. (6) (2007)
Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda
12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique. ISSCC (2007)
Nobuharu Kami, Jun Suzuki, Yoichi Hidaka, Takashi Yoshikawa, Atsushi Iwata
Multilayer In-service Reconfiguration for Network Computing Systems. NCA (2007)
Tomio Sato, Atsuki Inoue, Tetsuyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto, Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata
On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications. ISSCC (2007)
Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation. CICC (2007)
Kan'ya Sasaki, Seiji Kameda, Atsushi Iwata
Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated by Various Window Sizes. ACCV (2) (2006)
Atsushi Iwata
Carrier-Grade Ethernet Technologies for Next Generation Wide Area Ethernet. IEICE Trans. Commun. (3) (2006)
Takeshi Yoshida, Yoshihiro Masui, Takayuki Mashimo, Mamoru Sasaki, Atsushi Iwata
A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique. IEICE Trans. Electron. (6) (2006)
Hideo Yoshimi, Nobuyuki Enomoto, Chinryu Sai, Kazuo Takagi, Atsushi Iwata
Proposal & demonstration of a new remote home-access system, softwire. CCNC (2006)
Jun Suzuki, Yoichi Hidaka, Junichi Higuchi, Takashi Yoshikawa, Atsushi Iwata
ExpressEther - Ethernet-Based Virtualization Technology for Reconfigurable Hardware Platform. Hot Interconnects (2006)
Teppei Nakano, Takashi Morie, Hideaki Ishizu, Hiroshi Ando, Atsushi Iwata
FPGA Implementation of Resistive-Fuse Networks for Coarse Image-Region Segmentation. Intell. Autom. Soft Comput. 12 (3) (2006)
Tsutomu Yoshimura, Atsushi Iwata
A study of interference in synchronous systems. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2006)
Osamu Nomura, Takashi Morie, Keisuke Korekado, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
An Image-Filtering LSI Processor Architecture for Face/Object Recognition Using a Sorted Projection-Field Model Based on a Merged/Mixed Analog-Digital Architecture. IEICE Trans. Electron. (6) (2006)
Kan'ya Sasaki, Takashi Morie, Atsushi Iwata
A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory. IEICE Trans. Electron. (11) (2006)
Mitsuru Shiozaki, Mamoru Sasaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda
20GHz uniform-phase uniform-amplitude standing-wave clock distribution. IEICE Electron. Express 3 (2) (2006)
Masaki Umayabashi, Yoichi Hidaka, Nobuyuki Enomoto, Daisaku Ogasahara, Kazuo Takagi, Atsushi Iwata, Akira Arutaki
Improving Ethernet Reliability and Stability Using Global Open Ethernet Technology. IEICE Trans. Commun. (3) (2006)
Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata
A 1V supply successive approximation ADC with rail-to-rail input voltage range. ISCAS (1) (2005)
Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata
A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique. IEICE Trans. Electron. (6) (2005)
Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata
A Cellular-Automaton-Type Region Extraction Algorithm and its FPGA Implementation. J. Robotics Mechatronics 17 (4) (2005)
Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata
A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. ICNC (3) (2005)
Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata
A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors. J. Robotics Mechatronics 17 (4) (2005)
Tsutomu Yoshimura, Atsushi Iwata
An analysis of interference in synchronous systems. IEICE Electron. Express 1 (15) (2004)
Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. J. Intell. Fuzzy Syst. 15 (3-4) (2004)
Norihito Fujita, Yuichi Ishikawa, Atsushi Iwata, Rauf Izmailov
Coarse-grain replica management strategies for dynamic replication of Web contents. Comput. Networks 45 (1) (2004)
Atsushi Iwata, Yoichi Hidaka, Masaki Umayabashi, Nobuyuki Enomoto, Akira Arutaki
Global open ethernet (GOE) system and its performance evaluation. IEEE J. Sel. Areas Commun. 22 (8) (2004)
Aleksandar Kolarov, Bhaskar Sengupta, Atsushi Iwata
Design of multiple reverse spanning trees in next generation of Ethernet-VPNs. GLOBECOM (2004)
Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata
A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. KES (2004)
Takashi Morie, Jun Umezawa, Atsushi Iwata
Gabor-Type Filtering using Transient States of Cellular Neural Networks. Intell. Autom. Soft Comput. 10 (2) (2004)
Wen Kung Chu, Nishath K. Verghese, Heayn-Jun Chol, Kenji Shimazaki, Hiroyuki Tsujikawa, Shouzou Hirano, Shirou Doushoh, Makoto Nagata, Atsushi Iwata, Takafumi Ohmoto
A substrate noise analysis methodology for large-scale mixed-signal ICs. CICC (2003)
Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. KES (2003)
Kousuke Katayama, Atsushi Iwata
A High-Resolution CMOS Image Sensor with Hadamard Transform Function. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2003)
Hiroshi Ando, Takashi Morie, Makoto Miyake, Makoto Nagata, Atsushi Iwata
Image Segmentation/Extraction Using Nonlinear Cellular Networks and Their VLSI Implementation Using Pulse-Modulation Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2002)
Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. VLSI Design (2002)
Makoto Nagata, Takashi Morie, Atsushi Iwata
Modeling substrate noise generation in CMOS digital integrated circuits. CICC (2002)
Teppei Nakano, Takashi Morie, Makoto Nagata, Atsushi Iwata
A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. APCCAS (2) (2002)
Norihito Fujita, Nobuyuki Enomoto, Atsushi Iwata, Rauf Izmailov
Coarse-grain dynamic replication schemes for scalable content delivery networks. GLOBECOM (2002)
Norihito Fujita, Atsushi Iwata
Adaptive and efficient multiple path pre-computation for QoS routing protocols. GLOBECOM (2001)
Shigeo Kinoshita, Takashi Morie, Makoto Nagata, Atsushi Iwata
A PWM analog memory programming circuit for floating-gate MOSFETs with 75-μs programming time and 11-bit updating resolution. IEEE J. Solid State Circuits 36 (8) (2001)
Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata
Test circuits for substrate noise evaluation in CMOS digital ICs. ASP-DAC (2001)
Makoto Nagata, Jin Nagai, Katsumasa Hijikata, Takashi Morie, Atsushi Iwata
Physical design guides for substrate noise reduction in CMOS digital circuits. IEEE J. Solid State Circuits 36 (3) (2001)
Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata
An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. NIPS (2001)
Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. ISQED (2001)
Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata
Quantitative characterization of substrate noise for physical design guides in digital circuits. CICC (2000)
Rauf Izmailov, Atsushi Iwata, Bhaskar Sengupta
ATM Routing Algorithms for Multimedia Traffic in Private ATM Networks. J. Heuristics 6 (1) (2000)
Atsushi Iwata, Makoto Nagata, Noriaki Takeda, Mitsuru Homma, Takashi Morie
Pulse modulation circuit architecture and its application to functional image sensors. ISCAS (2000)
Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata
Measurements and analyses of substrate noise waveform inmixed-signal IC environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (6) (2000)
Atsushi Iwata, Norihito Fujita
A hierarchical multilayer QoS routing system with dynamic SLA management. IEEE J. Sel. Areas Commun. 18 (12) (2000)
Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata
An arbitrary chaos generator core curcuit using PWM/PPM signals. ASP-DAC (2000)
Makoto Nagata, Atsushi Iwata
Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. ASP-DAC (2000)
Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata
A smart imager for the vision processing front-END. ASP-DAC (2000)
Makoto Nagata, Yoji Kashima, Daisuke Tamura, Takashi Morie, Atsushi Iwata
Measurements and analyses of substrate noise waveform in mixed signal IC environment. CICC (1999)
Atsushi Iwata, Ching-Chuan Chiang, Guangyu Pei, Mario Gerla, Tsu-Wei Chen
Scalable routing strategies for ad hoc wireless networks. IEEE J. Sel. Areas Commun. 17 (8) (1999)
Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie
A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. VLSI (1999)
Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata
Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. ICONIP (1998)
Atsushi Iwata, Hiroshi Suzuki, Rauf Izmailov, Bhaskar Sengupta
QOS aggregation algorithms in hierarchical ATM networks. ICC (1998)
Makoto Nagata, Jun Funakoshi, Atsushi Iwata
A PWM signal processing core circuit based on a switched current integration technique. IEEE J. Solid State Circuits 33 (1) (1998)
Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata
Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. ICONIP (1998)
Atsushi Iwata, N. Mori, Chinatsu Ikeda, Hiroshi Suzuki, Maximilian Ott
ATM Connection and Traffic Management Schemes for Multimedia Internetworking. Commun. ACM 38 (2) (1995)
Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura, Atsushi Iwata
Oversampling A-to-D and D-to-A converters with multistage noise shaping modulators. IEEE Trans. Acoust. Speech Signal Process. 36 (12) (1988)
Takao Kaneko, Hironori Yamauchi, Atsushi Iwata
A 50ns floating-point signal processor VLSI. ICASSP (1986)
Kuniharu Uchimura, Toshio Hayashi, Tadakatsu Kimura, Atsushi Iwata
VLSI- A to D and D to A converters with multi-stage noise shaping modulators. ICASSP (1986)
Junichi Takahashi, Takashi Kimura, Sanshiro Hattori, Atsushi Iwata
A ring array processor architecture for highly parallel dynamic time warping. IEEE Trans. Acoust. Speech Signal Process. 34 (5) (1986)
Hironori Yamauchi, Takao Kaneko, Tsutomu Kobayashi, Atsushi Iwata, Sadayasu Ono
An 18-bit floating-point signal processor VLSI with an on-chip 512W dual-port RAM. ICASSP (1985)
Naohisa Ohta, Kazunari Irie, Takehiko Uno, Atsushi Iwata, Tomonori Aoyama
A high quality ADM LSI codec at 32 kbit/s for digital speech communications. ICASSP (1982)