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Yoshitaka Murasaka
Publication Activity (10 Years)
Years Active: 2001-2020
Publications (10 Years): 5
Top Topics
Focal Plane
Sampling Algorithm
Early Stage
Breast Cancer Detection
Top Venues
BioCAS
IEEE Trans. Biomed. Circuits Syst.
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Publications
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Takamaro Kikkawa
,
Yoshihiro Masui
,
Akihiro Toya
,
Hiroyuki Ito
,
Takuichi Hirano
,
Tomoaki Maeda
,
Masahiro Ono
,
Yoshitaka Murasaka
,
Toshifumi Imamura
,
Tsuyoshi Matsumaru
,
Michimasa Yamaguchi
,
Mitsutoshi Sugawara
,
Afreen Azhari
,
Hang Song
,
Shinsuke Sasada
,
Atsushi Iwata
CMOS Gaussian Monocycle Pulse Transceiver for Radar-Based Microwave Imaging.
IEEE Trans. Biomed. Circuits Syst.
14 (6) (2020)
Akihiro Toya
,
Takamaro Kikkawa
,
Yoshihiro Masui
,
Mitsutoshi Sugawara
,
Hiroyuki Ito
,
Tomoaki Maeda
,
Masahiro Ono
,
Yoshitaka Murasaka
,
Toshifumi Imamura
,
Atsushi Iwata
Shifting Clock Jitter and Phase Interval for Impulse-Radar-Based Breast Cancer Detection.
BioCAS
(2019)
Yoshihiro Masui
,
Akihiro Toya
,
Mitsutoshi Sugawara
,
Tomoaki Maeda
,
Masahiro Ono
,
Yoshitaka Murasaka
,
Atsushi Iwata
,
Takamaro Kikkawa
Gaussian Monocycle Pulse Generator with Calibration Circuit for Breast Cancer Detection.
BioCAS
(2018)
Yoshihiro Masui
,
Akihiro Toya
,
Mitsutoshi Sugawara
,
Tomoaki Maeda
,
Masahiro Ono
,
Yoshitaka Murasaka
,
Atsushi Iwata
,
Takamaro Kikkawa
Differential equivalent time sampling receiver for breast cancer detection.
BioCAS
(2017)
Akihiro Toya
,
Yoshihiro Masui
,
Mitsutoshi Sugawara
,
Tomoaki Maeda
,
Masahiro Ono
,
Yoshitaka Murasaka
,
Atsushi Iwata
,
Takamaro Kikkawa
Investigation of phase noise and jitter in CMOS sampling clock generation circuits for time-domain breast cancer detection system.
BioCAS
(2017)
Atsushi Iwata
,
Yoshitaka Murasaka
,
Tomoaki Maeda
,
Takafumi Ohmoto
Background Calibration Techniques for Low-Power and High-Speed Data Conversion.
IEICE Trans. Electron.
(6) (2011)
Daisuke Kosaka
,
Makoto Nagata
,
Yoshitaka Murasaka
,
Atsushi Iwata
Chip-Level Substrate Coupling Analysis with Reference Structures for Verification.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(12) (2007)
Daisuke Kosaka
,
Makoto Nagata
,
Yoshitaka Murasaka
,
Atsushi Iwata
Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(2) (2007)
Tomio Sato
,
Atsuki Inoue
,
Tetsuyoshi Shiota
,
Tomoko Inoue
,
Yukihito Kawabe
,
Tetsutaro Hashimoto
,
Toshifumi Imamura
,
Yoshitaka Murasaka
,
Makoto Nagata
,
Atsushi Iwata
On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications.
ISSCC
(2007)
Daisuke Kosaka
,
Makoto Nagata
,
Yoshitaka Murasaka
,
Atsushi Iwata
Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation.
CICC
(2007)
Makoto Nagata
,
Yoshitaka Murasaka
,
Youichi Nishimori
,
Takashi Morie
,
Atsushi Iwata
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models.
VLSI Design
(2002)
Yoshitaka Murasaka
,
Makoto Nagata
,
Takafumi Ohmoto
,
Takashi Morie
,
Atsushi Iwata
Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation.
ISQED
(2001)