Investigation of phase noise and jitter in CMOS sampling clock generation circuits for time-domain breast cancer detection system.
Akihiro ToyaYoshihiro MasuiMitsutoshi SugawaraTomoaki MaedaMasahiro OnoYoshitaka MurasakaAtsushi IwataTakamaro KikkawaPublished in: BioCAS (2017)
Keyphrases
- high speed
- breast cancer detection
- power consumption
- analog vlsi
- delay insensitive
- circuit design
- vlsi circuits
- power dissipation
- low power
- cmos technology
- breast cancer
- frequency domain
- low cost
- early stage
- chip design
- focal plane
- x ray
- power supply
- low voltage
- power reduction
- sample size
- sampling algorithm
- floating gate
- packet loss
- sampling methods
- logic synthesis
- random access memory
- parallel processing
- random sampling
- image segmentation