Low-Voltage and Low-Noise CMOS Analog Circuits Using Scaled Devices.

Atsushi Iwata Takeshi Yoshida Mamoru Sasaki

Published in: IEICE Trans. Electron. (2007)

Keyphrases

low voltage
analog circuits
cmos technology
design considerations
power line
fault diagnosis
digital circuits
random access memory
power dissipation
power management
neural network
power consumption
real time
genetic algorithm
low cost
parallel processing