Mitsuru Shiozaki

Publication Activity (10 Years)

Years Active: 2005-2023
Publications (10 Years): 14

Top Topics

Countermeasures

Encryption Decryption

Top Venues

IACR Cryptol. ePrint Arch.

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

J. Cryptogr. Eng.

Publications

Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino
Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino
Deep learning side-channel attack against hardware implementations of AES. Microprocess. Microsystems 87 (2021)
Mitsuru Shiozaki, Takeshi Fujino
Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF. J. Cryptogr. Eng. 11 (3) (2021)
Kota Yoshida, Mitsuru Shiozaki, Shunsuke Okura, Takaya Kubota, Takeshi Fujino
Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2021)
Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino
Exploring Effect of Residual Electric Charges on Cryptographic Circuits. ASHES@CCS (2020)
Kota Yoshida, Takaya Kubota, Shunsuke Okura, Mitsuru Shiozaki, Takeshi Fujino
Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator. ISCAS (2020)
Mitsuru Shiozaki, Yohei Hori, Takeshi Fujino
Entropy Estimation of Physically Unclonable Functions. IACR Cryptol. ePrint Arch. 2020 (2020)
Mitsuru Shiozaki, Yohei Hori, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino
Cause Analysis Method of Entropy Loss in Physically Unclonable Functions. ISCAS (2020)
Mitsuru Shiozaki, Takeshi Fujino
Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF. ASHES@CCS (2019)
Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino
Deep Learning Side-Channel Attack Against Hardware Implementations of AES. DSD (2019)
Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino
Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis. FCCM (2019)
Shunsuke Okura, Ryota Ishiki, Masayoshi Shirahata, Takaya Kubota, Mitsuru Shiozaki, Kenichiro Ishikawa, Isao Takayanagi, Takeshi Fujino
A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF. ISPACS (2018)
Takeshi Fujino, Takaya Kubota, Mitsuru Shiozaki
Tamper-resistant cryptographic hardware. IEICE Electron. Express 14 (2) (2017)
Mitsuru Shiozaki, Takaya Kubota, Masashi Nakano, Yuuki Nakazawa, Takeshi Fujino
Malicious CAN-message attack against advanced driving assistant system. HOST (2017)
Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
Reversing stealthy dopant-level circuits. J. Cryptogr. Eng. 5 (2) (2015)
Mitsuru Shiozaki, Takaya Kubota, Tsunato Nakai, Akihiro Takeuchi, Takashi Nishimura, Takeshi Fujino
Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM. ISCAS (2015)
Mitsuru Shiozaki, Ryohei Hori, Takeshi Fujino
Diffusion Programmable Device : The device to prevent reverse engineering. IACR Cryptol. ePrint Arch. 2014 (2014)
Tsunato Nakai, Megumi Shibatani, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino
Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks. ISCAS (2014)
Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino
Security Evaluation of RG-DTM PUF Using Machine Learning Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2014)
Koichi Shimizu, Daisuke Suzuki, Toyohiro Tsurumaru, Takeshi Sugawara, Mitsuru Shiozaki, Takeshi Fujino
Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2014)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
On measurable side-channel leaks inside ASIC design primitives. J. Cryptogr. Eng. 4 (1) (2014)
Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
Reversing Stealthy Dopant-Level Circuits. IACR Cryptol. ePrint Arch. 2014 (2014)
Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
Reversing Stealthy Dopant-Level Circuits. CHES (2014)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
On Measurable Side-Channel Leaks inside ASIC Design Primitives. IACR Cryptol. ePrint Arch. 2013 (2013)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
On Measurable Side-Channel Leaks Inside ASIC Design Primitives. CHES (2013)
Masato Taniguchi, Mitsuru Shiozaki, Hiroshi Kubo, Takeshi Fujino
A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications. GCCE (2013)
Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino
High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. IEICE Trans. Electron. (4) (2012)
Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. DSD (2012)
Katsuhiko Iwai, Mitsuru Shiozaki, Anh-Tuan Hoang, Kenji Kojima, Takeshi Fujino
Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL. HOST (2011)
Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino
The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement. ISCAS (2011)
Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda
12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique. ISSCC (2007)
Mitsuru Shiozaki, Mamoru Sasaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda
20GHz uniform-phase uniform-amplitude standing-wave clock distribution. IEICE Electron. Express 3 (2) (2006)
Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata
A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip Using Two-Step Synchronization Technique. IEICE Trans. Electron. (6) (2005)
Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki, Atsushi Iwata
A 2.7 Gcps and 7-Multiplexing CDMA Serial Communication Chip for Real-Time Robot Control with Multiprocessors. J. Robotics Mechatronics 17 (4) (2005)