Takeshi Fujino

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 44

Top Topics

Countermeasures

Software Implementation

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

J. Cryptogr. Eng.

Publications

Kota Yoshida, Takeshi Fujino
Model Extraction Attack Without Natural Images. ACNS Workshops (2) (2024)
Tatsuya Oyama, Kota Yoshida, Shunsuke Okura, Takeshi Fujino
Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (3) (2024)
Tatsuya Oyama, Mika Sakai, Yohei Hori, Toshihiro Katashita, Takeshi Fujino
FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks. ACNS Workshops (1) (2024)
Yuta Fukuda, Kota Yoshida, Takeshi Fujino
Incorporating Cluster Analysis of Feature Vectors for Non-profiled Deep-learning-Based Side-Channel Attacks. ACNS Workshops (1) (2024)
Tsunato Nakai, Ye Wang, Kota Yoshida, Takeshi Fujino
SEDMA: Self-Distillation with Model Aggregation for Membership Privacy. Proc. Priv. Enhancing Technol. 2024 (1) (2024)
Yuta Fukuda, Kota Yoshida, Hisashi Hashimoto, Kunihiro Kuroda, Takeshi Fujino
Profiling Deep Learning Side-Channel Attacks Using Multi-Label against AES Circuits with RSM Countermeasure. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Masato Okuda, Kota Yoshida, Takeshi Fujino
Multispectral Pedestrian Detection with Visible and Far-infrared Images Under Drifting Ambient Light and Temperature. SENSORS (2023)
Yuta Fukuda, Kota Yoshida, Takeshi Fujino
Evaluation of Model Quantization Method on Vitis-AI for Mitigating Adversarial Examples. IEEE Access 11 (2023)
Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino
Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. Sensors 23 (10) (2023)
Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino
Practical aspects on non-profiled deep-learning side-channel attacks against AES software implementation with two types of masking countermeasures including RSM. J. Cryptogr. Eng. 13 (4) (2023)
Rei Ueda, Tsunato Nakai, Kota Yoshida, Takeshi Fujino
Evaluation of Membership Inference Attack Against Federated Learning With Differential Privacy on Edge Devices. GCCE (2023)
Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino
Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106 (3) (2023)
Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino
Experimental Study of Fault Injection Attack on Image Sensor Interface for Triggering Backdoored DNN Models. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Kota Yoshida, Masaya Hojo, Takeshi Fujino
Adversarial Scan Attack against Scan Matching Algorithm for Pose Estimation in LiDAR-Based SLAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Seiya Shimada, Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino
Deep Learning-Based Side-Channel Attacks against Software-Implemented RSA using Binary Exponentiation with Dummy Multiplication. ATAIT (2022)
Yuta Fukuda, Kota Yoshida, Takeshi Fujino
Fault Injection Attacks Utilizing Waveform Pattern Matching against Neural Networks Processing on Microcontroller. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2022)
Madoka Sakou, Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino
Deep Learning Side-Channel Attacks against Hardware-Implemented Lightweight Cipher Midori 64. ATAIT (2022)
Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino
Towards Isolated AI Accelerators with OP-TEE on SoC-FPGAs. ACNS Workshops (2022)
Tatsuya Oyama, Kota Yoshida, Shunsuke Okura, Takeshi Fujino
Fundamental Study of Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface. AsianHOST (2022)
Shunsuke Okura, Masanori Aoki, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino, Kenichiro Ishikawa, Isao Takayanagi
Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor. Sensors 21 (18) (2021)
Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino
Deep learning side-channel attack against hardware implementations of AES. Microprocess. Microsystems 87 (2021)
Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino
Towards Trained Model Confidentiality and Integrity Using Trusted Execution Environments. ACNS Workshops (2021)
Mitsuru Shiozaki, Takeshi Fujino
Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF. J. Cryptogr. Eng. 11 (3) (2021)
Tsunato Nakai, Daisuke Suzuki, Fumio Omatsu, Takeshi Fujino
Adversarial Black-Box Attacks with Timing Side-Channel Leakage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2021)
Hiroshi Yamada, Shunsuke Okura, Masayoshi Shirahata, Takeshi Fujino
Modeling attacks against device authentication using CMOS image sensor PUF. IEICE Electron. Express 18 (7) (2021)
Tatsuya Oyama, Shunsuke Okura, Kota Yoshida, Takeshi Fujino
Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface. ASHES@CCS (2021)
Kota Yoshida, Mitsuru Shiozaki, Shunsuke Okura, Takaya Kubota, Takeshi Fujino
Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2021)
Tsunato Nakai, Daisuke Suzuki, Takeshi Fujino
Timing Black-Box Attacks: Crafting Adversarial Examples through Timing Leaks against DNNs on Embedded Devices. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021 (3) (2021)
Kota Yoshida, Kuniyasu Suzaki, Takeshi Fujino
Towards Trusted IoT Sensing Systems: Implementing PUF as Secure Key Generator for Root of Trust and Message Authentication Code. HASP@MICRO (2021)
Kota Yoshida, Takeshi Fujino
Model Evasion Attacks Against Partially Encrypted Deep Neural Networks in Isolated Execution Environment. ACNS Workshops (2021)
Kunihiro Kuroda, Yuta Fukuda, Kota Yoshida, Takeshi Fujino
Practical Aspects on Non-profiled Deep-learning Side-channel Attacks against AES Software Implementation with Two Types of Masking Countermeasures including RSM. ASHES@CCS (2021)
Yuta Fukuda, Kota Yoshida, Hisashi Hashimoto, Takeshi Fujino
Deep Learning Side-Channel Attacks Against Lightweight SCA Countermeasure RSM-AES. AsianHOST (2021)
Kota Yoshida, Takeshi Fujino
Disabling Backdoor and Identifying Poison Data by using Knowledge Distillation in Backdoor Attacks on Deep Neural Networks. AISec@CCS (2020)
Mitsuru Shiozaki, Takeshi Sugawara, Takeshi Fujino
Exploring Effect of Residual Electric Charges on Cryptographic Circuits. ASHES@CCS (2020)
Kota Yoshida, Takaya Kubota, Shunsuke Okura, Mitsuru Shiozaki, Takeshi Fujino
Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator. ISCAS (2020)
Mitsuru Shiozaki, Yohei Hori, Takeshi Fujino
Entropy Estimation of Physically Unclonable Functions. IACR Cryptol. ePrint Arch. 2020 (2020)
Mitsuru Shiozaki, Yohei Hori, Tatsuya Oyama, Masayoshi Shirahata, Takeshi Fujino
Cause Analysis Method of Entropy Loss in Physically Unclonable Functions. ISCAS (2020)
Mitsuru Shiozaki, Takeshi Fujino
Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF. ASHES@CCS (2019)
Takaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino
Deep Learning Side-Channel Attack Against Hardware Implementations of AES. DSD (2019)
Kota Yoshida, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino
Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis. FCCM (2019)
Shunsuke Okura, Ryota Ishiki, Masayoshi Shirahata, Takaya Kubota, Mitsuru Shiozaki, Kenichiro Ishikawa, Isao Takayanagi, Takeshi Fujino
A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF. ISPACS (2018)
Takeshi Fujino, Takaya Kubota, Mitsuru Shiozaki
Tamper-resistant cryptographic hardware. IEICE Electron. Express 14 (2) (2017)
Takeshi Kumaki, Takeshi Fujino
Hierarchical-Masked Image Filtering for Privacy-Protection. IEICE Trans. Inf. Syst. (10) (2017)
Mitsuru Shiozaki, Takaya Kubota, Masashi Nakano, Yuuki Nakazawa, Takeshi Fujino
Malicious CAN-message attack against advanced driving assistant system. HOST (2017)
Kyosuke Kageyama, Kohei Sugiyama, Takeshi Kumaki, Takeshi Fujino
Development of LED illumination-based spy photo-prevention system. GCCE (2015)
Kyosuke Kageyama, Kohei Sugiyama, Takeshi Kumaki, Takeshi Fujino
Proposal of LED-based Peeping Prevention System. MWSCAS (2015)
Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
Reversing stealthy dopant-level circuits. J. Cryptogr. Eng. 5 (2) (2015)
Mitsuru Shiozaki, Takaya Kubota, Tsunato Nakai, Akihiro Takeuchi, Takashi Nishimura, Takeshi Fujino
Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM. ISCAS (2015)
Takeshi Kumaki, Takeshi Fujino, Tetsushi Koide
Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor. APCCAS (2014)
Mitsuru Shiozaki, Ryohei Hori, Takeshi Fujino
Diffusion Programmable Device : The device to prevent reverse engineering. IACR Cryptol. ePrint Arch. 2014 (2014)
Anh-Tuan Hoang, Takeshi Fujino
Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA. ACM Trans. Reconfigurable Technol. Syst. 7 (2) (2014)
Tsunato Nakai, Megumi Shibatani, Mitsuru Shiozaki, Takaya Kubota, Takeshi Fujino
Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks. ISCAS (2014)
Yuki Yanagihara, Toshiya Honda, Takeshi Kumaki, Takeshi Fujino
Live Demonstration: Hierarchical masked image filtering technology on security-camera for privacy protection. ISCAS (2014)
Takeshi Kumaki, Kei Nakao, Kohei Hozumi, Takeshi Ogura, Takeshi Fujino
Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices. IEICE Trans. Inf. Syst. (3) (2014)
Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino
Security Evaluation of RG-DTM PUF Using Machine Learning Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2014)
Koichi Shimizu, Daisuke Suzuki, Toyohiro Tsurumaru, Takeshi Sugawara, Mitsuru Shiozaki, Takeshi Fujino
Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2014)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
On measurable side-channel leaks inside ASIC design primitives. J. Cryptogr. Eng. 4 (1) (2014)
Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
Reversing Stealthy Dopant-Level Circuits. IACR Cryptol. ePrint Arch. 2014 (2014)
Takeshi Sugawara, Daisuke Suzuki, Ryoichi Fujii, Shigeaki Tawa, Ryohei Hori, Mitsuru Shiozaki, Takeshi Fujino
Reversing Stealthy Dopant-Level Circuits. CHES (2014)
Toshiya Honda, Yuma Murakami, Yuki Yanagihara, Takeshi Kumaki, Takeshi Fujino
Hierarchical image-scrambling method with scramble-level controllability for privacy protection. MWSCAS (2013)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
On Measurable Side-Channel Leaks inside ASIC Design Primitives. IACR Cryptol. ePrint Arch. 2013 (2013)
Kei Nakao, Kohei Hozumi, Takeshi Kumaki, Takeshi Ogura, Takeshi Fujino
Development of effective information-hiding method for embedded systems. MWSCAS (2013)
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
On Measurable Side-Channel Leaks Inside ASIC Design Primitives. CHES (2013)
Anh-Tuan Hoang, Takeshi Fujino
Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only). FPGA (2013)
Masato Taniguchi, Mitsuru Shiozaki, Hiroshi Kubo, Takeshi Fujino
A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications. GCCE (2013)
Takeshi Kumaki, Masaya Yoshikawa, Takeshi Fujino
Cipher-destroying and secret-key-emitting hardware Trojan against AES core. MWSCAS (2013)
Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino
The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3. VLSI-DAT (2013)
Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino
Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino
High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications. IEICE Trans. Electron. (4) (2012)
Anh-Tuan Hoang, Takeshi Fujino
Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. FPGA (2012)
Hiroki Ito, Mitsuru Shiozaki, Anh-Tuan Hoang, Takeshi Fujino
Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit. DSD (2012)
Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka, Masaya Yoshikawa, Takeshi Fujino
Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2012)
Katsuhiko Iwai, Mitsuru Shiozaki, Anh-Tuan Hoang, Kenji Kojima, Takeshi Fujino
Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL. HOST (2011)
Masaya Yoshikawa, Takeshi Fujino
Placement Tool Dedicated for a Via-Programmable Logic Device VPEX. Int. J. Comput. Their Appl. 18 (4) (2011)
Kota Furuhashi, Mitsuru Shiozaki, Akitaka Fukushima, Takahiko Murayama, Takeshi Fujino
The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement. ISCAS (2011)
Masaya Yoshikawa, Yuichi Kokusyo, Takeshi Fujino
Placement Tool Dedicated for a Via-programmable Logic Device VPEX. CAINE (2010)
Akihiro Nakamura, Masahide Kawarasaki, Kouta Ishibashi, Masaya Yoshikawa, Takeshi Fujino
Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing. IEICE Trans. Electron. (4) (2008)
Akihiro Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, Takeshi Fujino
Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing. CICC (2007)
Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki
A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto
An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. IEEE J. Solid State Circuits 38 (11) (2003)
Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto
A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. IEEE J. Solid State Circuits 32 (11) (1997)