A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme.
Masaki TsukudeShigehiro KugeTakeshi FujinoKazutami ArimotoPublished in: IEEE J. Solid State Circuits (1997)
Keyphrases
- low power
- low voltage
- cmos technology
- power consumption
- high speed
- low cost
- energy dissipation
- high power
- single chip
- vlsi architecture
- wireless transmission
- vlsi circuits
- digital signal processing
- low power consumption
- mixed signal
- gate array
- logic circuits
- power management
- image sensor
- charge coupled device
- power system