Masaki Tsukude

Publication Activity (10 Years)

Years Active: 1989-1998
Publications (10 Years): 0

Publications

Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada
400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits 33 (5) (1998)
Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. IEEE J. Solid State Circuits 32 (3) (1997)
Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto
A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. IEEE J. Solid State Circuits 32 (11) (1997)
Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto
SOI-DRAM circuit technologies for low power high speed multigiga scale memories. IEEE J. Solid State Circuits 31 (4) (1996)
Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. IEEE J. Solid State Circuits 31 (11) (1996)
Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto
Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. IEEE J. Solid State Circuits 30 (11) (1995)
Mikio Asakura, Tsukasa Ooishi, Masaki Tsukude, Shigeki Tomishima, Takahisa Eimori, Hideto Hidaka, Yoshikazu Ohno, Kazutani Arimoto, Kazuyasu Fujishima, Tadashi Nishimura, Tsutomu Yoshihara
An experimental 256-Mb DRAM with boosted sense-ground scheme. IEEE J. Solid State Circuits 29 (11) (1994)
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. 10 (2) (1993)
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC (1992)
Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima
A New Array Architecture for Parallel Testing in VLSI Memories. ITC (1989)