Michihiro Yamada

Publication Activity (10 Years)

Years Active: 1985-2021
Publications (10 Years): 7

Top Topics

Mathematical Model

Evaluation Methodologies

Environmental Factors

Information Sharing

Top Venues

DPM/CBT@ESORICS

Publications

Hiroaki Kikuchi, Michihiro Yamada, Kazuki Ikegami, Koji Inui
Best Security Measures to Reduce Cyber-Incident and Data Breach Risks. DPM/CBT@ESORICS (2021)
Kazuki Ikegami, Michihiro Yamada, Hiroaki Kikuchi, Koji Inui
Development of a Cyber Incident Information Crawler. IMIS (2019)
Michihiro Yamada, Hiroaki Kikuchi, Naoki Matsuyama, Koji Inui
Mathematical Model to Estimate Loss by Cyber Incident in Japan. ICISSP (2019)
Michihiro Yamada, Riko Shigeno, Hiroaki Kikuchi, Maki Sakamoto
Evaluation and Development of Onomatopoeia CAPTCHAs. PST (2018)
Hiroaki Kikuchi, Koichi Niihara, Michihiro Yamada
How Much is Risk Increased by Sharing Credential in Group? STM (2017)
Koichi Niihara, Michihiro Yamada, Hiroaki Kikuchi
Sharing or Non-sharing Credentials: A Study of What Motivates People to Be Malicious Insiders. HCI (22) (2017)
Michihiro Yamada, Koichi Niihara, Hiroaki Kikuchi
Decision Tree Analysis on Environmental Factors of Insider Threats. HCI (30) (2017)
Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara
Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits 36 (1) (2001)
Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada
A 5.3-GB/s embedded SDRAM core with slight-boost scheme. IEEE J. Solid State Circuits 34 (5) (1999)
Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34 (4) (1999)
Hirotoshi Sato, Hideaki Nagaoka, Hiroaki Honda, Yukio Maki, Tomohisa Wada, Yutaka Arita, Kazuhito Tsutsumi, Makoto Taniguchi, Michihiro Yamada
A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell. IEEE J. Solid State Circuits 33 (11) (1998)
Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada
400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits 33 (5) (1998)
Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. IEEE J. Solid State Circuits 32 (3) (1997)
Yoshikazu Morooka, Shigeru Mori, Hiroshi Miyamoto, Michihiro Yamada
An Address Maskable Parallel Testing for Ultra High Density DRAMs. ITC (1991)
Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano
Test Pattern Considerations for Fault Tolerant High Density DRAM. ITC (1985)