Kazutami Arimoto

Publication Activity (10 Years)

Years Active: 1985-2023
Publications (10 Years): 20

Top Topics

Sensor Networks

Top Venues

IIAI-AAI-Winter

Publications

Tomoya Kubo, Tomoyuki Yokogawa, Kazutami Arimoto, Masaki Hokari, Isao Kayano
Enhancing the Generalization Performance of Drowsiness Estimation AI in Drivers Using Time-Series Data from FAUs with Limited Datasets. IIAI-AAI-Winter (2023)
Ryugo Tanaka, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto
Applying Symbolic Model Checking to Node-graph Style Game Scripts with Time Constraints. GCCE (2023)
Yuji Yano, Hisashi Iwamoto, Takuma Yoshimura, Yoshihiro Nishida, Tatsuya Mori, Kiyotaka Komoku, Hidekuni Takao, Kazutami Arimoto
28-m W Fully Embedded AI Techniques with On-site Learning for Low-Power Handy Tactile Sensing System. VLSI-DAT (2022)
Kazuki Wayama, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto
Verifying Game Logic in Unreal Engine 5 Blueprint Visual Scripting System Using Model Checking. ASE (2022)
Kazuma Toyota, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto
A Visual Modeling Environment for the nuXmv Model Checker Intended for Novice Users. IIAI-AAI (2022)
Hidekuni Takao, Kazuki Watatani, Kazutami Arimoto
New Value Creation by Nano-Tactile Sensor Chip Exceeding our Fingertip Discrimination Ability. HCS (2021)
Hiroshi Miyata, Kazutami Arimoto
Localized Data Transfer System by Vehicles and Cellular Base Station in Local Area. ICC Workshops (2021)
Nao Igawa, Tomoyuki Yokogawa, Sousuke Amasaki, Masafumi Kondo, Yoichiro Sato, Kazutami Arimoto
Symbolic Representation of Time Petri Nets for Efficient Bounded Model Checking. IEICE Trans. Inf. Syst. (3) (2020)
Hayato Naito, Tomoyuki Yokogawa, Nao Igawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto
A Node-Style Visual Programming Environment for the nuXmv Model Checker. GCCE (2020)
Tomoki Kobayashi, Tomoyuki Yokogawa, Nao Igawa, Yoichiro Sato, Kimihoro Sugino, Hiroshi Miyata, Satoshi Fujii, Kazutami Arimoto
A Edge Master Computing for Pineapple Monitoring System with Drone and Data-management. IIAI-AAI (2020)
Nao Igawa, Tomoyuki Yokogawa, Mami Takahashi, Kazutami Arimoto
Model Checking of Visual Scripts Created by UE4 Blueprints. IIAI-AAI (2020)
Tomoki Kobayashi, Tomoyuki Yokogawa, Nao Igawa, Yoichiro Sato, Satoshi Fujii, Kazutami Arimoto
A Compact Low Power AI Module Mounted on Drone for Plant Monitor System. IIAI-AAI (2019)
Akira Matsumoto, Tomoyuki Yokogawa, Sousuke Amasaki, Hirohisa Aman, Kazutami Arimoto
Consistency Verification of UML Sequence Diagrams Modeling Wireless Sensor Networks. IIAI-AAI (2019)
Satoshi Fujii, Issei Nakaema, Kei Miyagi, Shouichiro Tanifuji, Noriaki Yoshikawa, Kensaku Kinoshita, Kazutami Arimoto
Radio link design for ITS integrated network using drone. APWCS (2019)
Nao Igawa, Tomoyuki Yokogawa, Sousuke Amasaki, Kiyotaka Komoku, Yoichiro Sato, Kazutami Arimoto
Interpolation Based Unbounded Model Checking for Time Petri Nets. GCCE (2018)
Salilthip Phuklang, Tomoyuki Yokogawa, Pattara Leelaprute, Kazutami Arimoto
Tool Support for Consistency Verification of UML Diagrams. PROFES (2017)
Kazutami Arimoto, Daichi Yamashita, Nao Igawa, Tomoyuki Yokogawa, Yoichiro Sato, Isao Kayano, Akio Shiratori
A smart low power R-R-I heartbeat monitor system with contactless UWB sensor. ISOCC (2017)
Daichi Okamoto, Masafumi Kondo, Tomoyuki Yokogawa, Yoshihiro Sejima, Kazutami Arimoto, Yoichiro Sato
A Serial Booth Multiplier Using Ring Oscillator. CANDAR (2016)
Kiyotaka Komoku, Kazutami Arimoto, Tomoyuki Yokogawa, Hitoshi Yamauchi, Yoichiro Sato, Hidekuni Takao
processing architecture - High reliability and low power computing for novel nano tactile sensor array. ISOCC (2016)
Yoshifumi Kawamura, Naoya Okada, Yoshio Matsuda, Tetsuya Matsumura, Hiroshi Makino, Kazutami Arimoto
A Field Programmable Sequencer and Memory with Middle Grained Programmability Optimized for MCU Peripherals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2016)
Tomoyuki Yokogawa, Masafumi Kondo, Hisashi Miyazaki, Sousuke Amasaki, Yoichiro Sato, Kazutami Arimoto
Bounded model checking of Time Petri Nets using SAT solver. IEICE Electron. Express 12 (2) (2015)
Tetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda
The LSI implementation of a memory based field programmable device for MCU peripherals. DDECS (2014)
Woogeun Rhee, Gangadhar Burra, Kazutami Arimoto, Pieter Harpe, Brian Otis, David Ruffieux
F5: Low-power radios for sensor networks. ISSCC (2014)
Tomoyuki Yokogawa, Sousuke Amasaki, Keisuke Okazaki, Yoichiro Sato, Kazutami Arimoto, Hisashi Miyazaki
Consistency Verification of UML Diagrams Based on Process Bisimulation. PRDC (2013)
Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto
Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System. IEEE J. Solid State Circuits 48 (11) (2013)
Kazutami Arimoto, Sam Kavusi, Kenneth Salisbury
What's next in robots? ∼Sensing, processing, networking toward human brain and body. ISSCC (2012)
Yushi Moko, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa, Masami Nakajima, Kazutami Arimoto
Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G. CVPR Workshops (2011)
Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, Kazutami Arimoto
PEARL and PEACH: A Novel PCI Express Direct Link and Its Implementation. IPDPS Workshops (2011)
Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Yasushi Hayakawa, Takeshi Oshita, Satoshi Kaneko, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato
An 80Gb/s dependable communication SoC with PCI express I/F and 8 CPUs. ISSCC (2011)
Toru Shimizu, Kazutami Arimoto, Osamu Nishii, Sugako Otani, Hiroyuki Kondo
Low Power Platform for Embedded Processor LSIs. IEICE Trans. Electron. (4) (2011)
Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
A Scalable Massively Parallel Processor for Real-Time Image Processing. IEEE J. Solid State Circuits 46 (10) (2011)
Sugako Otani, Hiroyuki Kondo, Itaru Nonomura, Atsuyuki Ikeya, Minoru Uemura, Katsushi Asahina, Kazutami Arimoto, Shin'ichi Miura, Toshihiro Hanawa, Taisuke Boku, Mitsuhisa Sato
An 80 Gbps dependable multicore communication SoC with PCI express I/F and intelligent interrupt controller. COOL Chips (2011)
Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
A scalable massively parallel processor for real-time image processing. ISSCC (2010)
Koji Nii, Makoto Yabuuchi, Hidehiro Fujiwara, Hirofumi Nakano, Kazuya Ishihara, Hiroyuki Kawai, Kazutami Arimoto
Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation. SoCC (2010)
Toshihiro Hanawa, Taisuke Boku, Shin'ichi Miura, Mitsuhisa Sato, Kazutami Arimoto
PEARL: Power-Aware, Dependable, and High-Performance Communication Link Using PCI Express. GreenCom/CPSCom (2010)
Satoshi Shigematsu, Kazutami Arimoto, Christoph Hagleitner
Fusion of MEMS and circuits. ISSCC (2010)
Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto
A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. IEICE Trans. Electron. (4) (2009)
Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu
Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications. IEEE J. Solid State Circuits 44 (8) (2009)
Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto
On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. IEICE Trans. Electron. (3) (2009)
Hiroyuki Kondo, Masami Nakajima, Sugako Otani, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Kazuhiro Inaoka, Yoshihiro Saito, Kazutami Arimoto, Toru Shimizu
Heterogeneous multicore SoC for secure multimedia applications. CICC (2008)
Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors. IEEE J. Solid State Circuits 43 (4) (2008)
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. (9) (2008)
Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto
The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits 42 (4) (2007)
Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS (2007)
Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto
A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. IEICE Trans. Electron. (10) (2007)
Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL (2007)
Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. (1) (2007)
Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. IEEE J. Solid State Circuits 42 (4) (2007)
Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. IEICE Trans. Electron. (4) (2007)
Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto
A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. ISSCC (2007)
Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. IEEE J. Solid State Circuits 42 (11) (2007)
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. (8) (2007)
Fukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Trans. Electron. (4) (2007)
Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture. IEEE J. Solid State Circuits 42 (1) (2007)
Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka
A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. CICC (2006)
Takayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba
An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC Design. IEICE Trans. Electron. (11) (2006)
Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu
A 40GOPS 250mW massively parallel processor based on matrix architecture. ISSCC (2006)
Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. (11) (2006)
Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. (4) (2005)
Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40 (1) (2005)
Hideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto
A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAM. CICC (2005)
Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. (6) (2005)
Masahisa Iida, Naoki Kuroda, Hidefumi Otsuka, Masanobu Hirose, Yuji Yamasaki, Kiyoto Ohta, Kazuhiko Shimakawa, Takashi Nakabayashi, Hiroyuki Yamauchi, Tomohiko Sano, Takayuki Gyohten, Masanao Maruta, Akira Yamazaki, Fukashi Morishita, Katsumi Dosaka, Masahiko Takeuchi, Kazutami Arimoto
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning. IEEE J. Solid State Circuits 40 (11) (2005)
Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) (2005)
Akira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros. IEICE Trans. Electron. (10) (2005)
Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
A capacitorless twin-transistor random access memory (TTRAM) on SOI. CICC (2005)
Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta, Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo, Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. IEEE J. Solid State Circuits 40 (1) (2005)
Takeshi Fujino, Akira Yamazaki, Yasuhiko Taito, Mitsuya Kinoshita, Fukashi Morishita, Teruhiko Amano, Masaru Haraguchi, Makoto Hatakenaka, Atsushi Amo, Atsushi Hachisuka, Kazutami Arimoto, Hideyuki Ozaki
A Low Power Embedded DRAM Macro for Battery-Operated LSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Yasuhiko Taito, Tetsushi Tanizaki, Mitsuya Kinoshita, Futoshi Igaue, Takeshi Fujino, Kazutami Arimoto
An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write. IEEE J. Solid State Circuits 38 (11) (2003)
Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara
Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits 36 (1) (2001)
Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada
Test cost reduction by at-speed BISR for embedded DRAMs. ITC (2001)
Tadaaki Yamauchi, Fukashi Morishita, Shigenobu Maeda, Kazutami Arimoto, Kazuyasu Fujishima, Hideyuki Ozaki, Tsutomu Yoshihara
High-performance embedded SOI DRAM architecture for the low-power supply. IEEE J. Solid State Circuits 35 (8) (2000)
Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada
A 5.3-GB/s embedded SDRAM core with slight-boost scheme. IEEE J. Solid State Circuits 34 (5) (1999)
Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada
400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits 33 (5) (1998)
Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada
High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. IEEE J. Solid State Circuits 32 (3) (1997)
Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma
A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. IEEE J. Solid State Circuits 32 (11) (1997)
Masaki Tsukude, Shigehiro Kuge, Takeshi Fujino, Kazutami Arimoto
A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme. IEEE J. Solid State Circuits 32 (11) (1997)
Shigehiro Kuge, Fukashi Morishita, Takahiro Tsuruda, Shigeki Tomishima, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto
SOI-DRAM circuit technologies for low power high speed multigiga scale memories. IEEE J. Solid State Circuits 31 (4) (1996)
Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. IEEE J. Solid State Circuits 31 (11) (1996)
Tadato Yamagata, Shigeki Tomishima, Masaki Tsukude, Takahiro Tsuruda, Yasushi Hashizume, Kazutami Arimoto
Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs. IEEE J. Solid State Circuits 30 (11) (1995)
Tsukasa Ooishi, Mikio Asakura, Shigeki Tomishima, Hideto Hidaka, Kazutami Arimoto, Kazuyasu Fujishima
A well-synchronized sensing/equalizing method for sub-1.0-V operating advanced DRAMs. IEEE J. Solid State Circuits 29 (4) (1994)
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsuhiro Suma, Kazuyasu Fujishima
Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters. IEEE Des. Test Comput. 10 (2) (1993)
Masaki Tsukude, Kazutami Arimoto, Hideto Hidaka, Yasuhiro Konishi, Masanori Hayashikoshi, Katsunori Suma, Kazuyasu Fujishima
A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter. ITC (1992)
Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima
A New Array Architecture for Parallel Testing in VLSI Memories. ITC (1989)
Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, T. Nakano
Test Pattern Considerations for Fault Tolerant High Density DRAM. ITC (1985)