Kazunari Inoue

Publication Activity (10 Years)

Years Active: 1995-2019
Publications (10 Years): 4

Top Topics

Security Enforcement

Top Venues

IEICE Trans. Commun.

ACM SIGOPS Oper. Syst. Rev.

Publications

Kazunari Inoue, Nozomi Kobori, Atsushi Hirota, Tetsushi Koide, Takumi Okamoto
An IoT-gateway with the information-centric communication. ISDCS (2019)
Kazunari Inoue, Yuji Yano
A large scale access-control list for IoT security comprising embedded IP-core and DDR DRAM. ISOCC (2016)
Masami Nawa, Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka
Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure. CCNC (2016)
Atsushi Ooka, Shingo Ata, Kazunari Inoue, Masayuki Murata
High-Speed Design of Conflictless Name Lookup and Efficient Selective Cache on CCN Router. IEICE Trans. Commun. (4) (2015)
Atsushi Ooka, Shingo Ata, Kazunari Inoue, Masayuki Murata
Design of a high-speed content-centric-networking router using content addressable memory. INFOCOM Workshops (2014)
Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Kazunari Inoue, Ikuo Oka
A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application. IEICE Trans. Electron. (8) (2013)
Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue
Deterministic Packet Buffer System with Multi FIFO Queues for the Advanced QoS. IEICE Trans. Commun. (7) (2013)
Sou Koyano, Shingo Ata, Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Kazunari Inoue, Ikuo Oka
A study on micro level traffic prediction for energy-aware routers. ACM SIGOPS Oper. Syst. Rev. 47 (3) (2013)
Kenzo Okuda, Shingo Ata, Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Kazunari Inoue, Ikuo Oka
2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving. CCNC (2013)
Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka
FPS-RAM: Fast Prefix Search RAM-Based Hardware for Forwarding Engine. IEICE Trans. Commun. (7) (2012)
Sou Koyano, Shingo Ata, Ikuo Oka, Kazunari Inoue
A High-Grained Traffic Prediction for Microseconds Power Control in Energy-Aware Routers. UCC (2012)
Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto, Kazunari Inoue, Masahiro Suzuki
A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application. CICC (2012)
Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto, Shingo Ata, Kazunari Inoue
Deterministic High Density Packet-Buffer System for Low Cost Network Systems. AINA (2012)
Yuji Yano, Hisashi Iwamoto, Yasuto Kuroda, Shiro Ohtani, Shingo Ata, Kazunari Inoue
A slice structure using the management of network traffic prediction for green IT. HPSR (2012)
Kazuya Zaitsu, Koji Yamamoto, Yasuto Kuroda, Kazunari Inoue, Shingo Ata, Ikuo Oka
Hardware implementation of fast forwarding engine using standard memory and dedicated circuit. ICECS (2010)
Haesung Hwang, Shingo Ata, Koji Yamamoto, Kazunari Inoue, Masayuki Murata
A New TCAM Architecture for Managing ACL in Routers. IEICE Trans. Commun. (11) (2010)
Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. (4) (2005)
Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40 (1) (2005)
Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. (6) (2005)
Kazunari Inoue, Hisashi Nakamura, Hiroyuki Kawai
A 10 Mb frame buffer memory with Z-compare and A-blend units. IEEE J. Solid State Circuits 30 (12) (1995)
Masaki Kumanoya, Toshiyuki Ogawa, Kazunari Inoue
Advances in DRAM interfaces. IEEE Micro 15 (6) (1995)