Hans Jürgen Mattausch

ORCID

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 45

Top Venues

ISDCS

IEICE Trans. Electron.

IEEE Access

ESSDERC

Publications

Aiwen Luo, Sandip Bhattacharya, Mitiko Miura-Mattausch, Yicong Zhou, Hans Jürgen Mattausch
Real-Time Surface Identification System for Variable Walking Speeds of Biped Robots. IEEE Embed. Syst. Lett. 16 (2) (2024)
Tapas K. Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Electro-mechanical Model and its Application to biped-robot stability with force Sensors. Int. J. Robotics Autom. 37 (4) (2022)
Mitiko Miura-Mattausch, Hideyuki Kikuchihara, Hans Jürgen Mattausch
Model Development for Robust Design of SOI-MOSFET Circuits used in Radiative Environments. ISDCS (2021)
Hideyuki Kikuchihara, Mitiko Miura-Mattausch, Takeshi Mizoguchi, Hajime Nagase, Makoto Hashimoto, Yusuke Kawaguchi, Hans Jürgen Mattausch
Modeling of SJ-MOSFET for High-Voltage Applications with Inclusion of Carrier Dynamics during Switching. ISDCS (2021)
Abhishek Kar, Mitiko Miura-Mattausch, Mainak Sengupta, Dondee Navarro, Hideyuki Kikuchihara, Takahiro Iizuka, Hafizur Rahaman, Hans Jürgen Mattausch
Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation. IEEE Access 9 (2021)
Sandip Bhattacharya, Aiwen Luo, Sunandan Dutta, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Force-Sensor-Based Surface Recognition With Surface-Property-Dependent Walking-Speed Adjustment of Humanoid Robot. IEEE Access 8 (2020)
Fernando Ávila Herrera, Mitiko Miura-Mattausch, Takahiro Iizuka, Hideyuki Kikuchihara, Yoko Hirano, Hans Jürgen Mattausch
Modeling of Short-Channel Effect on Multi-Gate MOSFETs for Circuit Simulation. ISDCS (2020)
Sandip Bhattacharya, Sunandan Dutta, Aiwen Luo, Mitiko Miura-Mattausch, Yoshihiro Ochi, Hans Jürgen Mattausch
Energy Efficiency of Force-Sensor-Controlled Humanoid-Robot Walking on Indoor Surfaces. IEEE Access 8 (2020)
Sunandan Dutta, Mitiko Miura-Mattausch, Yoshihiro Ochi, Naoto Yorino, Hans Jürgen Mattausch
Gyro-Sensor-Based Vibration Control for Dynamic Humanoid-Robot Walking on Inclined Surfaces. Sensors 20 (24) (2020)
Kenshiro Sato, Dondee Navarro, Shinya Sekizaki, Yoshifumi Zoka, Naoto Yorino, Hans Jürgen Mattausch, Mitiko Miura-Mattausch
Prediction of DC-AC Converter Efficiency Degradation due to Device Aging Using a Compact MOSFET-Aging Model. IEICE Trans. Electron. (3) (2020)
Hans Jürgen Mattausch, Aiwen Luo, Sunandan Dutta, Sunandan Dutta, Tapas K. Maiti, Mitiko Miura-Mattausch
Force-Sensor-Based Walking-Environment Recognition of Biped Robots. ISDCS (2020)
Sunandan Dutta, Tapas Kumar Maiti, Mitiko Miura-Mattausch, Yoshihiro Ochi, Naoto Yorino, Hans Jürgen Mattausch
Analysis of Sensor-Based Real-Time Balancing of Humanoid Robots on Inclined Surfaces. IEEE Access 8 (2020)
S. Bhattacharya, Aiwen Luo, Sunandan Dutta, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Surface Recognition and Speed Adjustment of Humanoid Robot Using External Control Circuit. ISDCS (2020)
Soumajit Ghosh, Mitiko Miura-Mattausch, Takahiro Iizuka, Hideyuki Kikuchihara, Hafizur Rahaman, Hans Jürgen Mattausch
History Effect on Circuit Performance of SOI-MOSFETs. ISDCS (2020)
Arnab Mukhopadhyay, Tapas Kumar Maiti, Sandip Bhattacharya, Takahiro Iizuka, Hideyuki Kikuchihara, Mitiko Miura-Mattausch, Hafizur Rahaman, Sadayuki Yoshitomi, Dondee Navarro, Hans Jürgen Mattausch
Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs. IEICE Trans. Electron. (6) (2019)
Nezam Rohbani, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka
NVDL-Cache: Narrow-Width Value Aware Variable Delay Low-Power Data Cache. ICCD (2019)
Aiwen Luo, Sandip Bhattacharya, Tapas Kumar Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Dynamic Pattern-Recognition-Based Walking-Speed Adjustment for Stable Biped-Robot Movement under Changing Surface Conditions. GCCE (2019)
Yosuke Miyaoku, Mitiko Miura-Mattausch, Akihiro Tone, Hans Jürgen Mattausch, Kai Matsuura, Daisaku Ikoma
Analysis of IGBT Charging/Discharging Mechanism for Accurate Compact Modeling. ISDCS (2019)
Takao Yamamoto, Yukiya Fukunaga, Daisaku Ikoma, Mitiko Miura-Mattausch, Dondee Navarro, Hans Jürgen Mattausch
Analysis of Embedded-Diode Performance in MOSFET under Switching Condition. ISDCS (2019)
Sunandan Dutta, Tapas K. Maiti, Yoshihiro Ochi, Mitiko Miura-Mattausch, Sandip Bhattacharya, Naoto Yorino, Hans Jürgen Mattausch
Stability Analysis of Humanoid Robots with Gyro Sensors Subjected to External Push Forces. ISDCS (2019)
Jungang Guan, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
Energy-Efficient Hardware Implementation of Road-Lane Detection Based on Hough Transform with Parallelized Voting Procedure and Local Maximum Algorithm. IEICE Trans. Inf. Syst. (6) (2019)
Takahiro Iizuka, Hiroyuki Hashigami, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Validation on Duality in Impact-ionization Carrier Generation at the Onset of Snapback in Power MOSFETs. ISDCS (2019)
Nezam Rohbani, Hiroaki Gau, Sara Mohammadinejad, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka
Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values. IEEE Trans. Very Large Scale Integr. Syst. 27 (7) (2019)
Sandip Bhattacharya, Aiwen Luo, Tapas Kumar Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Surface-Property Recognition With Force Sensors for Stable Walking of Humanoid Robot. IEEE Access 7 (2019)
Aiwen Luo, Fengwei An, Xiangyu Zhang, Hans Jürgen Mattausch
A Hardware-Efficient Recognition Accelerator Using Haar-Like Feature and SVM Classifier. IEEE Access 7 (2019)
Tapas K. Maiti, Sunandan Dutta, Yoshihiro Ochi, Mitiko Miura-Mattausch, Sandip Bhattacharya, Hans Jürgen Mattausch
Power Consumption Estimation of Biped Robot During Walking. ISDCS (2019)
Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Tapas K. Maiti, Nezam Rohbani, Dondee Navarro, Hans Jürgen Mattausch
Compact modeling of dynamic trap density evolution for predicting circuit-performance aging. Microelectron. Reliab. 80 (2018)
Sunandan Dutta, Tapas K. Maiti, Yoshihiro Ochi, Mitiko Miura-Mattausch, Sandip Bhattacharya, Dondee Navarro, Naoto Yorino, Hans Jürgen Mattausch
Self-controlled walking robot with gyro sensor network for stable movement on non-smooth surfaces. SIMPAR (2018)
Fengwei An, Xiangyu Zhang, Aiwen Luo, Lei Chen, Hans Jürgen Mattausch
A Hardware Architecture for Cell-Based Feature-Extraction and Classification Using Dual-Feature Space. IEEE Trans. Circuits Syst. Video Technol. 28 (10) (2018)
Aiwen Luo, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26 (3) (2018)
Mitiko Miura-Mattausch, Hideyuki Kikuchihara, Tahahiro Kajiwara, Yuta Tanimoto, Atsushi Saito, Takahiro Iizuka, Dondee Navarro, Hans Jürgen Mattausch
Compact Modeling for Power Efficient Circuit Design. ESSDERC (2018)
Sandip Bhattacharya, Aiwen Luo, Tapas K. Maiti, Sunandan Dutta, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Fast Recognition and Control of Walking Mode for Humanoid Robot Based on Pressure Sensors and Nearest Neighbor Search. ISPACS (2018)
Xiangyu Zhang, Fengwei An, Lei Chen, Idaku Ishii, Hans Jürgen Mattausch
A Modular and Reconfigurable Pipeline Architecture for Learning Vector Quantization. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2018)
Takeshi Mizoguchi, Toshiyuki Naka, Yuta Tanimoto, Yasuhiro Okada, Wataru Saito, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Modeling of Field-Plate Effect on Gallium-Nitride-Based High Electron Mobility Transistors for High-Power Applications. IEICE Trans. Electron. (3) (2017)
Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Dondee Navarro, Tapas K. Maiti, Nezam Rohbani, C. Ma, Hans Jürgen Mattausch, A. Schiffmann, Alexander Steinmair, Ehrenfried Seebacher
Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits. ESSDERC (2017)
Tapas K. Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Compact modeling approach for electro-mechanical system simulation. ASICON (2017)
Jungang Guan, Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
Real-Time Straight-Line Detection for XGA-Size Videos by Hough Transform with Parallelized Voting Procedures. Sensors 17 (2) (2017)
Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
Dynamically reconfigurable system for LVQ-based on-chip learning and recognition. ISCAS (2016)
Yuki Fujita, Fengwei An, Aiwen Luo, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
Pixel-based pipeline hardware architecture for high-performance Haar-like feature extraction. APCCAS (2016)
Fengwei An, Lei Chen, Toshinobu Akazawa, Shogo Yamazaki, Hans Jürgen Mattausch
k Nearest Neighbor Classification Coprocessor with Weighted Clock-Mapping-Based Searching. IEICE Trans. Electron. (3) (2016)
Fengwei An, Xiangyu Zhang, Lei Chen, Hans Jürgen Mattausch
A Memory-Based Modular Architecture for SOM and LVQ with Dynamic Configuration. IEEE Trans. Multi Scale Comput. Syst. 2 (4) (2016)
Lei Chen, Tapas Kumar Maiti, Hidenori Miyamoto, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Actuator-Control Circuit Based on OTFTs and Flow-Rate Estimation for an All-Organic Fluid Pump. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2016)
Atsushi Saito, Kenshiro Sato, Yuta Tanimoto, Kai Matsuura, Yutaka Sasaki, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Yoshifumi Zoka
Efficiency Analysis of SiC-MOSFET-Based Bidirectional Isolated DC/DC Converters. IEICE Trans. Electron. (9) (2016)
Fengwei An, Keisuke Mihara, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch
Word-parallel associative memory for k-nearest-neighbor with configurable storage space of reference vectors. A-SSCC (2015)
Tapas Kumar Maiti, Lei Chen, Hidenori Miyamoto, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Mixed-domain compact modeling framework for fluid flow driven by electrostatic organic actuators. ESSDERC (2015)
Fengwei An, Lei Chen, Hans Jürgen Mattausch
A SoPC architecture for nearest-neighbor based learning and recognition. ISPACS (2014)
Indra Bagus Wicaksono, Fengwei An, Hans Jürgen Mattausch
Memory-based hardware-accelerated system for high-speed human detection. Adv. Robotics 28 (5) (2014)
Takao Yamamoto, Masataka Miyake, Uwe Feldmann, Hans Jürgen Mattausch, Mitiko Miura-Mattausch
Compact Modeling of Injection Enhanced Insulated Gate Bipolar Transistor Valid for Optimization of Switching Frequency. IEICE Trans. Electron. (10) (2014)
Fengwei An, Toshinobu Akazawa, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch
A coprocessor for clock-mapping-based nearest Euclidean distance search with feature vector dimension adaptability. CICC (2014)
Fengwei An, Toshinobu Akazawa, Shogo Yamazaki, Lei Chen, Hans Jürgen Mattausch
LVQ neural network SoC adaptable to different on-chip learning and recognition applications. APCCAS (2014)
Fengwei An, Hans Jürgen Mattausch
K-means clustering algorithm for multimedia applications with flexible HW/SW co-design. J. Syst. Archit. 59 (3) (2013)
Chenyue Ma, Hans Jürgen Mattausch, Masataka Miyake, Takahiro Iizuka, Kazuya Matsuzawa, Seiichiro Yamaguchi, Teruhiko Hoshida, Akinori Kinoshita, Takahiko Arakawa, Jin He, Mitiko Miura-Mattausch
Modeling of NBTI Stress Induced Hole-Trapping and Interface-State-Generation Mechanisms under a Wide Range of Bias Conditions. IEICE Trans. Electron. (10) (2013)
Takahiro Iizuka, Kenji Fukushima, Akihiro Tanaka, Hideyuki Kikuchihara, Masataka Miyake, Hans Jürgen Mattausch, Mitiko Miura-Mattausch
Modeling of Trench-Gate Type HV-MOSFETs for Circuit Simulation. IEICE Trans. Electron. (5) (2013)
Toshinobu Akazawa, Seiryu Sasaki, Hans Jürgen Mattausch
Word-parallel coprocessor architecture for digital nearest Euclidean distance search. ESSCIRC (2013)
Seiryu Sasaki, Masahiro Yasuda, Hans Jürgen Mattausch
Digital associative memory for word-parrallel Manhattan-distance-based vector quantization. ESSCIRC (2012)
Fengwei An, Hans Jürgen Mattausch
Cluster-Based Prototype Learning System for Multiple Applications with Flexible HW/SW Codesign. PDCAT (2012)
Indra Bagus Wicaksono, Fengwei An, Hans Jürgen Mattausch
Human recognition with a hardware-accelerated multi-prototype learning and classification system. ROBIO (2012)
Hans Jürgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi Koide
Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping. IEEE J. Solid State Circuits 47 (6) (2012)
Takahiro Iizuka, Takashi Sakuda, Yasunori Oritsuki, Akihiro Tanaka, Masataka Miyake, Hideyuki Kikuchihara, Uwe Feldmann, Hans Jürgen Mattausch, Mitiko Miura-Mattausch
Compact Modeling of Expansion Effects in LDMOS. IEICE Trans. Electron. (11) (2012)
Fengwei An, Tetsushi Koide, Hans Jürgen Mattausch
A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching. IEICE Trans. Inf. Syst. (9) (2012)
Norio Sadachika, Shu Mimura, Akihiro Yumisaki, Koh Johguchi, Akihiro Kaya, Mitiko Miura-Mattausch, Hans Jürgen Mattausch
Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design. IEICE Trans. Electron. (3) (2011)
Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide
Real-time hybrid learning and recognition system with software-hardware cooperation. ROBIO (2011)
Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Masaharu Tagami, Masakatsu Ishizaki
Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems. IEICE Trans. Inf. Syst. (9) (2011)
Ali Ahmadi, Hans Jürgen Mattausch, Md. Anwarul Abedin, Mahmoud Saeidi, Tetsushi Koide
An associative memory-based learning model with an efficient hardware implementation in FPGA. Expert Syst. Appl. 38 (4) (2011)
Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
A Scalable Massively Parallel Processor for Real-Time Image Processing. IEEE J. Solid State Circuits 46 (10) (2011)
Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika
Measurement-Based Ring Oscillator Variation Analysis. IEEE Des. Test Comput. 27 (5) (2010)
Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
A scalable massively parallel processor for real-time image processing. ISSCC (2010)
Tetsushi Koide, R. Kimura, T. Sugahara, K. Okazaki, Hans Jürgen Mattausch
Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size. ICNC (2010)
Akio Kawabata, Tetsushi Koide, Hans Jürgen Mattausch
Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding. ICNC (2010)
Hans Jürgen Mattausch, Wataru Imafuku, Tania Ansari, Akio Kawabata, Tetsushi Koide
Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. ESSCIRC (2010)
Masataka Miyake, Daisuke Hori, Norio Sadachika, Uwe Feldmann, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Takahiro Iizuka, Kazuya Matsuzawa, Yasuyuki Sahara, Teruhiko Hoshida, Toshiro Tsukada
Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation. IEICE Trans. Electron. (5) (2009)
Masataka Miyake, Daisuke Hori, Norio Sadachika, Uwe Feldmann, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shunsuke Miyamoto
Degraded Frequency-Tuning Range and Oscillation Amplitude of LC-VCOs due to the Nonquasi-Static Effect in MOS Varactors. IEICE Trans. Electron. (6) (2009)
Norio Sadachika, Takahiro Murakami, Hideki Oka, Ryou Tanabe, Hans Jürgen Mattausch, Mitiko Miura-Mattausch
Compact Double-Gate Metal-Oxide-Semiconductor Field Effect Transistor Model for Device/Circuit Optimization. IEICE Trans. Electron. (8) (2008)
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. (9) (2008)
Tatsuya Ezaki, Dondee Navarro, Youichi Takeda, Norio Sadachika, Gaku Suzuki, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto
Non-quasi-static approach with surface-potential-based MOSFET model HiSIM for RF circuit simulations. Math. Comput. Simul. 79 (4) (2008)
Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS (2007)
Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Trans. Electron. (11) (2007)
Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. ESSCIRC (2007)
Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. (1) (2007)
Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. IEICE Trans. Inf. Syst. (1) (2007)
Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Shogo Sakakibara, Tetsushi Koide, Hans Jürgen Mattausch
Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2007)
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. (8) (2007)
Koh Johguchi, Yuya Mukuda, Ken-ichi Aoyama, Hans Jürgen Mattausch, Tetsushi Koide
A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin. IEICE Electron. Express 4 (2) (2007)
Takeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch
Application of Multi-ported CAM for Parallel Coding. APCCAS (2006)
Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS (2006)
Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Tetsushi Koide, Hans Jürgen Mattausch
Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. APCCAS (2006)
Takashi Morimoto, Hidekazu Adachi, Osamu Kiriyama, Tetsushi Koide, Hans Jürgen Mattausch
Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. IEICE Trans. Inf. Syst. (3) (2006)
Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch
Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. ISCAS (2006)
Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. (11) (2006)
Takashi Morimoto, Hidekazu Adachi, Kousuke Yamaoka, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch
An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. APCCAS (2006)
Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. ASP-DAC (2006)
Ali Ahmadi, M. Arifin Ritonga, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide
A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA. IEEE Congress on Evolutionary Computation (2006)
Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. (4) (2005)
Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40 (1) (2005)
Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch
A low-power video segmentation LSI with boundary-active-only architecture. ASP-DAC (2005)
Dondee Navarro, Takeshi Mizoguchi, Masami Suetake, Kazuya Hisamitsu, Hiroaki Ueno, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential. IEICE Trans. Electron. (5) (2005)
Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. (6) (2005)
Shizunori Matsumoto, Hiroaki Ueno, Satoshi Hosokawa, Toshihiko Kitamura, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama
-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation. IEICE Trans. Electron. (2) (2005)
Takashi Morimoto, Osamu Kiriyama, Yohmei Harada, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
Object tracking in video pictures based on image segmentation and pattern matching. ISCAS (4) (2005)
Youichi Takeda, Dondee Navarro, Shingo Chiba, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Takahiro Iizuka, Masahiko Taguchi, Shigetaka Kumashiro, Shunsuke Miyamoto
MOSFET harmonic distortion analysis up to the non-quasi-static frequency regime. CICC (2005)

Hans Jürgen Mattausch.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Hans Jürgen Mattausch