Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory.
Takeshi KumakiYutaka KonoMasakatsu IshizakiTetsushi KoideHans Jürgen MattauschPublished in: IEICE Trans. Inf. Syst. (2007)
Keyphrases
- hardware architecture
- hardware implementation
- xilinx virtex
- processing elements
- parallel architecture
- content addressable memory
- fpga technology
- pipelined architecture
- table lookup
- field programmable gate array
- hardware design
- efficient implementation
- signal processing
- reconfigurable hardware
- fpga device
- parallel processing
- shared memory
- design methodology
- grid structure
- coding scheme
- parallel implementation
- parallel computing
- shape from shading
- single chip
- associative memory
- embedded systems
- massively parallel
- image processing algorithms