Tetsushi Koide

Publication Activity (10 Years)

Years Active: 1992-2022
Publications (10 Years): 22

Top Venues

ISDCS

CoRR

EMBC

ISCAS

Publications

Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Toru Tamaki, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
Classification with CNN features and SVM on Embedded DSP Core for Colorectal Magnified NBI Endoscopic Video Image. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2022)
Masayuki Odagawa, Tetsushi Koide, Toru Tamaki, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
Feasibility Study for Computer-Aided Diagnosis System with Navigation Function of Clear Region for Real-Time Endoscopic Video Image on Customizable Embedded DSP Cores. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2022)
Tetsushi Koide, Ryuichi Michida, Seiji Izakura, Yuki Hayashida, Yumi Aoyama
Sweat Droplets Detection Using Image Segmentation on Skin Surface for Evaluation of Sweating Responses to Thermal Stimulus in Atopic Dermatitis. MWSCAS (2021)
Ryuichi Michida, Seiji Izakura, Tetsushi Koide, Yuki Hayashida, Yumi Aoyama
An Image Segmentation Method for Automatic Analysis of Skin Surface Structure in Atopic Dermatitis by the Impression Mold Technique. MWSCAS (2021)
Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka, Takayuki Sugawara, Hiroshi Toishi, Masayuki Tsuji, Nobuo Tamba
A Hardware Implementation on Customizable Embedded DSP Core for Colorectal Tumor Classification with Endoscopic Video toward Real-Time Computer-Aided Diagnosais System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2021)
Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shinji Tanaka
Classification Method with CNN features and SVM for Computer-Aided Diagnosis System in Colorectal Magnified NBI Endoscopy. TENCON (2020)
Kyosuke Kageyama, Kensuke Watanabe, Akimitsu Hamai, Takeshi Kumaki, Tetsushi Koide
Acceleration of arithmetic processing with CAM-based massive-parallel SIMD matrix core. MWSCAS (2020)
Hideki Murakami, Yoshiki Tanaka, Jun-ichi Yamashita, Rikako Takeshita, Yasunori Sakane, Takumi Okamoto, Tetsushi Koide
Development of In-situ Monitoring System for Crop Growth Observation. ISDCS (2019)
Masayuki Odagawa, Takumi Okamoto, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka, Takayuki Sugawara, Hiroshi Toishi, Masayuki Tsuji, Nobuo Tamba
A Hardware Implementation of Colorectal Tumor Classification for Endoscopic Video on Customizable DSP Toward Real-Time Computer-Aided Diagnosis System. ISCAS (2019)
Kyosuke Kageyama, Takeshi Kumaki, Tetsushi Koide
Structuring Element-counting Approach for Morphological Pattern Spectrum-based Image Manipulation Detection. ISDCS (2019)
Kazunari Inoue, Nozomi Kobori, Atsushi Hirota, Tetsushi Koide, Takumi Okamoto
An IoT-gateway with the information-centric communication. ISDCS (2019)
Takumi Okamoto, Masayuki Odagawa, Tetsushi Koide, Shinji Tanaka, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shigeto Yoshida, Hiroshi Mieno
Feature Extraction of Colorectal Endoscopic Images for Computer-Aided Diagnosis with CNN. ISDCS (2019)
Toshihiro Kasama, Tetsushi Koide, Wojciech P. Bula, Yukio Yaji, Yoshishige Endo, Ryo Miyake
Low Cost and Robust Field-Deployable Environmental Sensor for Smart Agriculture. ISDCS (2019)
Takumi Okamoto, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Hiroshi Toishi, Takayuki Sugawara, Masayuki Tsuji, Masayuki Odagawa, Nobuo Tamba, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Shinji Tanaka
Implementation of Computer-Aided Diagnosis System on Customizable DSP Core for Colorectal Endoscopic Images with CNN Features and SVM. TENCON (2018)
Takumi Okamoto, Yasunori Sakane, Tetsushi Koide, Atsushi Ogawa, Masashi Komine, Chiharu Sone, Yoshihiro Kaneta, Yukio Yaji, Kyoko Toyofuku, Takahiro Kamata, Ken Kimura, Yoko Ishikawa, Toshihiro Kasama, Wojciech-Piptr Bula, Yoshishige Endo, Ryo Miyake
An Image Analysis Method for Lettuce Leaf and Root Growth Analysis in Hydroponic Culture. TENCON (2018)
Tsubasa Hirakawa, Toru Tamaki, Takio Kurita, Bisser Raytchev, Kazufumi Kaneda, Chaohui Wang, Laurent Najman, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
Discriminative Subtree Selection for NBI Endoscopic Image Labeling. ACCV Workshops (2) (2016)
Toru Tamaki, Shoji Sonoyama, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
Computer-Aided Colorectal Tumor Classification in NBI Endoscopy Using CNN Features. CoRR (2016)
Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
Development of a Real-time Colorectal Tumor Classification System for Narrow-band Imaging zoom-videoendoscopy. CoRR (2016)
Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Yoko Kominami, Shinji Tanaka
Corrigendum to "Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition" [Artif. Intell. Med. 68 (March 2016) 1-16]. Artif. Intell. Medicine 72 (2016)
Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Yoko Kominami, Shinji Tanaka
Defocus-aware Dirichlet particle filter for stable endoscopic video frame recognition. Artif. Intell. Medicine 68 (2016)
Toru Tamaki, Shoji Sonoyama, Takio Kurita, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka, Kazuaki Chayama
Domain Adaptation with L2 constraints for classifying images from different endoscope systems. CoRR (2016)
Shoji Sonoyama, Toru Tamaki, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
Transfer Learning for Endoscopic Image Classification. CoRR (2016)
Shoji Sonoyama, Toru Tamaki, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka
Trade-off between speed and performance for colorectal endoscopic NBI image classification. Medical Imaging: Image Processing (2015)
Takumi Okamoto, Tetsushi Koide, Koki Sugi, Tatsuya Shimizu, Anh-Tuan Hoang, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Shigeto Yoshida, Hiroshi Mieno, Shinji Tanaka
Image segmentation of pyramid style identifier based on Support Vector Machine for colorectal endoscopic images. EMBC (2015)
Shoji Sonoyama, Tsubasa Hirakawa, Toru Tamaki, Takio Kurita, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeto Yoshida, Yoko Kominami, Shinji Tanaka
Transfer learning for Bag-of-Visual words approach to NBI endoscopic image classification. EMBC (2015)
Takeshi Kumaki, Takeshi Fujino, Tetsushi Koide
Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor. APCCAS (2014)
Tetsushi Koide, Anh-Tuan Hoang, Takumi Okamoto, Satoshi Shigemi, Tsubasa Mishima, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka
FPGA implementation of type identifier for colorectal endoscopie images with NBI magnification. APCCAS (2014)
Tsubasa Hirakawa, Tom Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Yoko Kominami, Shigeto Yoshida, Shinji Tanaka
SVM-MRF segmentation of colorectal NBI endoscopic images. EMBC (2014)
Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto, Mutsumi Omori
Pipeline scanning architecture with computation reduction for rectangle pattern matching in real-time traffic sign detection. ISCAS (2014)
Anh-Tuan Hoang, Tetsushi Koide, Masaharu Yamamoto
Low cost hardware implementation for traffic sign detection system. APCCAS (2014)
Masaharu Yamamoto, Anh-Tuan Hoang, Mutsumi Omori, Tetsushi Koide
Compact hardware oriented number recognition algorithm for real-time speed traffic-sign recognition. ISCAS (2014)
Tsubasa Mishima, Satoshi Shigemi, Anh-Tuan Hoang, Tetsushi Koide, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka
FPGA implementation of feature extraction for colorectal endoscopic images with NBI magnification. ISCAS (2014)
Keisuke Konishi, Takeshi Tanaka, Tetsushi Koide
Power electronics education using the integrated circuit consistent education system and TCAD. FIE (2013)
Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Shigeta Yoshida, Yoko Kominami, Taiji Matsuo, Rie Miyaki, Shinji Tanaka
Labeling colorectal NBI zoom-videoendoscope image sequences with MRF and SVM. EMBC (2013)
Tsubasa Hirakawa, Toru Tamaki, Bisser Raytchev, Kazufumi Kaneda, Tetsushi Koide, Yoko Kominami, Rie Miyaki, Taiji Matsuo, Shigeto Yoshida, Shinji Tanaka
Smoothing posterior probabilities with a particle filter of dirichlet distribution for stabilizing colorectal NBI endoscopy recognition. ICIP (2013)
Hans Jürgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi Koide
Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping. IEEE J. Solid State Circuits 47 (6) (2012)
Fengwei An, Tetsushi Koide, Hans Jürgen Mattausch
A K-Means-Based Multi-Prototype High-Speed Learning System with FPGA-Implemented Coprocessor for 1-NN Searching. IEICE Trans. Inf. Syst. (9) (2012)
Fengwei An, Hans Jürgen Mattausch, Tetsushi Koide
Real-time hybrid learning and recognition system with software-hardware cooperation. ROBIO (2011)
Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Masaharu Tagami, Masakatsu Ishizaki
Software-Based Parallel Cryptographic Solution with Massive-Parallel Memory-Embedded SIMD Matrix Architecture for Data-Storage Systems. IEICE Trans. Inf. Syst. (9) (2011)
Ali Ahmadi, Hans Jürgen Mattausch, Md. Anwarul Abedin, Mahmoud Saeidi, Tetsushi Koide
An associative memory-based learning model with an efficient hardware implementation in FPGA. Expert Syst. Appl. 38 (4) (2011)
Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
A Scalable Massively Parallel Processor for Real-Time Image Processing. IEEE J. Solid State Circuits 46 (10) (2011)
Koh Johguchi, Akihiro Kaya, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide, Norio Sadachika
Measurement-Based Ring Oscillator Variation Analysis. IEEE Des. Test Comput. 27 (5) (2010)
Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Takayuki Gyohten, Tetsu Nishijima, Hiroyuki Yamasaki, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Yoshihiro Okuno, Tetsushi Koide, Hans Jürgen Mattausch, Kazutami Arimoto
A scalable massively parallel processor for real-time image processing. ISSCC (2010)
Tetsushi Koide, R. Kimura, T. Sugahara, K. Okazaki, Hans Jürgen Mattausch
Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size. ICNC (2010)
Akio Kawabata, Tetsushi Koide, Hans Jürgen Mattausch
Optimization Vector Quantization by Adaptive Associative-Memory-Based Codebook Learning in Combination with Huffman Coding. ICNC (2010)
Hans Jürgen Mattausch, Wataru Imafuku, Tania Ansari, Akio Kawabata, Tetsushi Koide
Low-power word-parallel nearest-Hamming-distance search circuit based on frequency mapping. ESSCIRC (2010)
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor. IEICE Trans. Electron. (9) (2008)
Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. ISCAS (2007)
Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka
4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words. IEICE Trans. Electron. (11) (2007)
Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Jürgen Mattausch, Tetsushi Koide
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme. ESSCIRC (2007)
Takeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer. IEICE Trans. Inf. Syst. (1) (2007)
Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch
Scalable FPGA/ASIC Implementation Architecture for Parallel Table-Lookup-Coding Using Multi-Ported Content Addressable Memory. IEICE Trans. Inf. Syst. (1) (2007)
Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Shogo Sakakibara, Tetsushi Koide, Hans Jürgen Mattausch
Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2007)
Takeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor. IEICE Trans. Inf. Syst. (8) (2007)
Koh Johguchi, Yuya Mukuda, Ken-ichi Aoyama, Hans Jürgen Mattausch, Tetsushi Koide
A 2-stage-pipelined 16 port SRAM with 590Gbps random access bandwidth and large noise margin. IEICE Electron. Express 4 (2) (2007)
Takeshi Kumaki, Y. Kouno, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch
Application of Multi-ported CAM for Parallel Coding. APCCAS (2006)
Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS (2006)
Md. Anwarul Abedin, Yuki Tanaka, Ali Ahmadi, Tetsushi Koide, Hans Jürgen Mattausch
Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. APCCAS (2006)
Takashi Morimoto, Hidekazu Adachi, Osamu Kiriyama, Tetsushi Koide, Hans Jürgen Mattausch
Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video-Segmentation. IEICE Trans. Inf. Syst. (3) (2006)
Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch
Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. ISCAS (2006)
Hideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto
A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC. IEICE Trans. Electron. (11) (2006)
Takashi Morimoto, Hidekazu Adachi, Kousuke Yamaoka, Kazutoshi Awane, Tetsushi Koide, Hans Jürgen Mattausch
An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. APCCAS (2006)
Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. ASP-DAC (2006)
Ali Ahmadi, M. Arifin Ritonga, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide
A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA. IEEE Congress on Evolutionary Computation (2006)
Hideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh. IEICE Trans. Electron. (4) (2005)
Hideyuki Noda, Kazunari Inoue, Masayuki Kuroiwa, Futoshi Igaue, Kouji Yamamoto, Hans Jürgen Mattausch, Tetsushi Koide, Atsushi Amo, Atsushi Hachisuka, Shinya Soeda, Isamu Hayashi, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara
A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture. IEEE J. Solid State Circuits 40 (1) (2005)
Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch
A low-power video segmentation LSI with boundary-active-only architecture. ASP-DAC (2005)
Kazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide
A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction Features. IEICE Trans. Electron. (6) (2005)
Takashi Morimoto, Osamu Kiriyama, Yohmei Harada, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
Object tracking in video pictures based on image segmentation and pattern matching. ISCAS (4) (2005)
Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide
Chip size and performance evaluations of shared cache for on-chip multiprocessor. Systems and Computers in Japan 36 (9) (2005)
Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. ISCAS (5) (2005)
Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch
Design of superscalar processor with multi-bank register file. ISCAS (4) (2005)
Ali Ahmadi, Md. Anwarul Abedin, Hans Jürgen Mattausch, Tetsushi Koide
A parallel hardware design for parametric active contour models. AVSS (2005)
Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ASP-DAC (2004)
Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch
Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. ASP-DAC (2004)
Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch
350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. ASP-DAC (2004)
Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch
Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation. IEICE Trans. Inf. Syst. (2) (2004)
Tetsushi Koide, Hans Jürgen Mattausch, Yuji Yano, Takayuki Gyohten, Yoshihiro Soda
A nearest-hamming-distance search memory with fully parallel mixed digital-analog match circuitry. ASP-DAC (2003)
Zhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka
A novel hierarchical multi-port cache. ESSCIRC (2003)
Shinya Yamasaki, Shingo Nakaya, Shin'ichi Wakabayashi, Tetsushi Koide
A Performance-Driven Floorplanning Method with Interconnect Performance Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Shigeki Takekawa, Shin'ichi Wakabayashi, Tetsushi Koide
A coterie-based mutual exclusion algorithm for distributed systems allowing multiple process failures at arbitrary time. Systems and Computers in Japan 33 (12) (2002)
Hans Jürgen Mattausch, Takayuki Gyohten, Yoshihiro Soda, Tetsushi Koide
Compact associative-memory architecture with fully parallel search capability for the minimum Hamming distance. IEEE J. Solid State Circuits 37 (2) (2002)
Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
Adaptation of genetic operators and parameters of a genetic algorithm based on the elite degree of an individual. Systems and Computers in Japan 32 (1) (2001)
Tetsushi Koide, S. Shinmori, H. Ishii
Topological optimization with a network reliability constraint. Discret. Appl. Math. 115 (1-3) (2001)
Takahiro Deguchi, Tetsushi Koide, Shin'ichi Wakabayashi
Timing-driven hierarchical global routing with wire-sizing and buffer-insertion for VLSI with multi-routing-layer. ASP-DAC (2000)
Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Masataka Yamane, Hajime Ueno
Genetic algorithm accelerator GAA-II. ASP-DAC (2000)
Shingo Nakaya, Tetsushi Koide, Shin'ichi Wakabayashi
An adaptive genetic algorithm for VLSI floorplanning based on sequence-pair. ISCAS (2000)
Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. ASP-DAC (1999)
Tetsushi Koide, Shin'ichi Wakabayashi
A timing-driven floorplanning algorithm with the Elmore delay model for building block layout. Integr. 27 (1) (1999)
Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. ASP-DAC (1999)
Tetsushi Koide, Shin'ichi Wakabayashi
A Timing-Driven Global Routing Algorithm with Pin Assignment, Block Reshaping, and Positioning for Building Block Layout. ASP-DAC (1998)
Koichi Hatta, Masashige Suzuki, Shin'ichi Wakabayashi, Tetsushi Koide
Solving the Capacitor Placement Problem in a Radial Distribution System Using an Adaptive Genetic Algorithm. PPSN (1998)
Tetsushi Koide, Shin'ichi Wakabayashi, Mitsuhiro Ono, Yutaka Nishimaru, Noriyoshi Yoshida
A timing-driven placement algorithm with the Elmore delay model for row-based VLSIs. Integr. 24 (1) (1997)
Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru
Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. ASP-DAC (1997)
Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
Pin assignment with global routing for VLSI building block layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (12) (1996)
Tetsushi Koide, Masahiro Tsuchiya, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A three-layer over-the-cell multi-channel router for a new cell model. Integr. 21 (3) (1996)
Tetsuya Miyoshi, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
An MCM Routing Algorithm Considering Crosstalk. ISCAS (1995)
Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A three-layer over-cell multi-channel routing method for a new cell model. ASP-DAC (1995)
Toshihiro Nakaoa, Shin'ichi Wakabayashi, Tetsushi Koide, Noriyoshi Yoshida
A Verification Algorithm for Logic Circuits with Internal Variables. ISCAS (1995)
Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida
A new system partitioning method under performance and physical constraints for multi-chip modules. ASP-DAC (1995)

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Publication Activity (10 Years)

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Tetsushi Koide