Kazuya Tanigawa

Publication Activity (10 Years)

Years Active: 2002-2015
Publications (10 Years): 1

Top Topics

Physical Design

Top Venues

IEICE Trans. Inf. Syst.

Publications

Ryo Okuda, Tomohiro Tanaka, Keisuke Yamamoto, Takumu Yahagi, Kazuya Tanigawa
Development of a Trax Artificial Intelligence algorithm using path and edge. FPT (2015)
Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro
A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks. IEICE Trans. Inf. Syst. (2) (2012)
Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro
EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. ReConFig (2011)
Kazuya Tanigawa, Tetsuo Hironaka
Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area. ISOCC (2011)
Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka
Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. ARC (2010)
Kazuya Tanigawa, Tetsuya Zuyama, Takuro Uchida, Tetsuo Hironaka
Exploring compact design on high throughput coarse grained reconfigurable architectures. FPL (2008)
Kazuya Tanigawa, Tetsuo Hironaka
Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation. FPT (2008)
Koh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa
Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. APCCAS (2006)
Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch
Design of superscalar processor with multi-bank register file. ISCAS (4) (2005)
Kazuya Tanigawa, Takashi Kawasaki, Tetsuo Hironaka
A coarse-grained reconfigurable architecture with low cost configuration data compression mechanism. FPT (2003)
Kazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida
A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the Model. FPL (2002)