Masato Inagi

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 5

Top Topics

Feature Vectors

Kullback Leibler Distance

Fpga Implementation

Approximate Nearest Neighbor

Top Venues

IPSJ Trans. Syst. LSI Des. Methodol.

Inf. Media Technol.

IPDPS Workshops

Publications

Gaku Kataoka, Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection. IPSJ Trans. Syst. LSI Des. Methodol. 16 (2023)
Gaku Kataoka, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
Novel Feature Vectors Considering Distances between Wires for Lithography Hotspot Detection. DSD (2018)
Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
An Approximate Nearest Neighbor Search Algorithm Using Distance-Based Hashing. DEXA (2) (2018)
Toshitaka Ito, Yuri Itotani, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
A Nearest Neighbor Search Engine Using Distance-Based Hashing. FPT (2018)
Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
An efficient FPGA implementation of Mahalanobis distance-based outlier detection for streaming data. FPT (2016)
Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. Inf. Media Technol. 9 (4) (2014)
Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko
An ILP-Based Optimal Circuit Mapping Method for PLDs. IPDPS Workshops (2014)
Yoichi Wakaba, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi
An Area Efficient Regular Expression Matching Engine Using Partial Reconfiguration for Quick Pattern Updating. IPSJ Trans. Syst. LSI Des. Methodol. 7 (2014)
Yoichi Wakaba, Shinobu Nagayama, Shin'ichi Wakabayashi, Masato Inagi
A Flexible and Compact Regular Expression Matching Engine Using Partial Reconfiguration for FPGA. DSD (2013)
Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi
A Multithreaded Parallel Global Routing Method with Overlapped Routing Regions. DSD (2013)
Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro
A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch Blocks. IEICE Trans. Inf. Syst. (2) (2012)
Yoichi Wakaba, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators. FPL (2011)
Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro
EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable Architecture. ReConFig (2011)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. FPL (2009)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. ISCAS (2008)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2007)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. FPT (2006)
Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani
An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2002)