Atsushi Takahashi

Publication Activity (10 Years)

Years Active: 1991-2024
Publications (10 Years): 18

Top Topics

Design Automation

Optimization Algorithm

Similarity Metrics

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IPSJ Trans. Syst. LSI Des. Methodol.

Publications

Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi
BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem. ISCAS (2024)
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka
Two-layer Bottleneck Channel Track Assignment for Analog VLSI. IPSJ Trans. Syst. LSI Des. Methodol. 17 (2024)
Atsushi Takahashi
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 16 (2023)
Atsushi Takahashi
Report on the 28th Asia and South Pacific Design Automation Conference. IEEE Des. Test 40 (3) (2023)
Atsushi Takahashi
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 15 (2022)
Atsushi Takahashi
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 14 (2021)
Atsushi Takahashi
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 13 (2020)
Shimpei Sato, Kano Akagi, Atsushi Takahashi
A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2020)
Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi
A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi
A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution. ISCAS (2019)
Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. ISVLSI (2018)
Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama
A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama
A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling. IEEE Trans. Very Large Scale Integr. Syst. 25 (3) (2017)
Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama
Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement. IPSJ Trans. Syst. LSI Des. Methodol. 10 (2017)
Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama
Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern. DATE (2016)
Yukihide Kohira, Atsushi Takahashi, Tomomi Matsui, Chikaaki Kodama, Shigeki Nojima, Satoshi Tanaka
Manufacturability-aware mask assignment in multiple patterning lithography. APCCAS (2016)
Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama
A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama
A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation. DATE (2016)
Yuta Nakatani, Atsushi Takahashi
A Length Matching Routing Algorithm for Set-Pair Routing Problem. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Fumiharu Nakajima, Shigeki Nojima, Toshiya Kotani, Takeshi Ihara, Atsushi Takahashi
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (5) (2015)
Takeshi Ihara, Atsushi Takahashi, Chikaaki Kodama
Effective two-dimensional pattern generation for self-aligned double patterning. ISCAS (2015)
Yukihide Kohira, Tomomi Matsui, Yoko Yokoyama, Chikaaki Kodama, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka
Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography. ASP-DAC (2015)
Tomomi Matsui, Yukihide Kohira, Chikaaki Kodama, Atsushi Takahashi
Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography. ISAAC (2014)
Yukihide Kohira, Atsushi Takahashi
2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Yukihide Kohira, Atsushi Takahashi
2-SAT based linear time optimum two-domain clock skew scheduling. ASP-DAC (2014)
Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama
A fast process variation and pattern fidelity aware mask optimization algorithm. ICCAD (2014)
Yiqiang Sheng, Atsushi Takahashi
A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2014)
Yiqiang Sheng, Atsushi Takahashi
A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization. Inf. Media Technol. 8 (4) (2013)
Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto, Atsushi Takahashi
Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control. ASP-DAC (2013)
Yiqiang Sheng, Atsushi Takahashi
A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization. IPSJ Trans. Syst. LSI Des. Methodol. 6 (2013)
Atsushi Takahashi
Dawn of computer-aided design: from graph-theory to place and route. ISPD (2013)
Yukihide Kohira, Atsushi Takahashi
An any-angle routing method using quasi-Newton method. ASP-DAC (2012)
Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno
RRA-based multi-objective optimization to mitigate the worst cases of placement. ASICON (2011)
Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi
Single-Layer Trunk Routing Using Minimal 45-Degree Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Atsushi Takahashi
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno
Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement. ISVLSI (2011)
Yukihide Kohira, Atsushi Takahashi
CAFE router: a fast connectivity aware multiple nets routing algorithm for routing grid with obstacles. ASP-DAC (2010)
Yukihide Kohira, Atsushi Takahashi
CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Yoichi Tomioka, Yoshiaki Kurata, Yukihide Kohira, Atsushi Takahashi
MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi
A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi
A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound. ASP-DAC (2009)
Yoichi Tomioka, Atsushi Takahashi
Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2009)
Yukihide Kohira, Shuhei Tani, Atsushi Takahashi
Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Yukihide Kohira, Atsushi Takahashi
A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2008)
Yoichi Tomioka, Atsushi Takahashi
A semi-monotonic routing method for fanin type Ball Grid Array packages. APCCAS (2008)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. ISCAS (2008)
Yukihide Kohira, Shuhei Tani, Atsushi Takahashi
Minimization of delay insertion in clock period improvement in general-synchronous framework. APCCAS (2008)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi
A Fast Clock Scheduling for Peak Power Reduction in LSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Yoichi Tomioka, Atsushi Takahashi
Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages. ASP-DAC (2008)
Yukihide Kohira, Atsushi Takahashi
A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework. ISCAS (2007)
Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi
A fast clock scheduling for peak power reduction in LSI. ACM Great Lakes Symposium on VLSI (2007)
Yukihide Kohira, Atsushi Takahashi
Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2007)
Bakhtiar Affendi Rosdi, Atsushi Takahashi
Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Yukiko Kubo, Atsushi Takahashi
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (4) (2006)
Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi
Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. ISCAS (2006)
Bakhtiar Affendi Rosdi, Atsushi Takahashi
Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits. APCCAS (2006)
Bakhtiar Affendi Rosdi, Atsushi Takahashi
Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Yoichi Tomioka, Atsushi Takahashi
Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Bakhtiar Affendi Rosdi, Atsushi Takahashi
Low area pipelined circuits by multi-clock cycle paths and clock scheduling. ASP-DAC (2006)
Yoichi Tomioka, Atsushi Takahashi
Monotonic parallel and orthogonal routing for single-layer ball grid array packages. ASP-DAC (2006)
Atsushi Takahashi
Practical Fast Clock-Schedule Design Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Yukiko Kubo, Atsushi Takahashi
A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2005)
Yukihide Kohira, Atsushi Takahashi
Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2005)
Yukiko Kubo, Atsushi Takahashi
A global routing method for 2-layer ball grid array packages. ISPD (2005)
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
Optimal integer delay-budget assignment on directed acyclic graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (8) (2004)
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
Incremental Timing Budget Management in Programmable Systems. ERSA (2004)
Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh
Optimal integer delay budgeting on directed acyclic graphs. DAC (2003)
Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi
A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani
An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (3) (2002)
Seiichiro Ishijima, Tetsuaki Utsumi, Tomohiro Oto, Atsushi Takahashi
A Semi-Synchronous Circuit Design Method by Clock Tree Modification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Keiichi Kurokawa, Takuya Yasui, Yoichi Matsumura, Masahiko Toyonaga, Atsushi Takahashi
A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Hidetoshi Matsumura, Atsushi Takahashi
Delay variation tolerant clock scheduling for semi-synchronous circuits. APCCAS (1) (2002)
Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi
Clustering based fast clock scheduling for light clock-tree. DATE (2001)
Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake
Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. VLSI Design (2000)
Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi
A practical clock tree synthesis for semi-synchronous circuits. ISPD (2000)
Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. ASP-DAC (1999)
Kengo R. Azegami, Atsushi Takahashi, Y. Kajitan
Enumerating the min-cuts for applications to graph extraction under size constraints. ISCAS (6) (1999)
Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani
Air-Pressure-Model-Based Fast Algorithms for General Floorplan. ASP-DAC (1998)
Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. ICCAD (1997)
Atsushi Takahashi, Yoji Kajitani
Performance and reliability driven clock scheduling of sequential logic circuits. ASP-DAC (1997)
Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani
Detailed-Routability of FPGAs with Extremal Switch-Block Structures. ED&TC (1996)
Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
Mixed Searching and Proper-Path-Width. Theor. Comput. Sci. 137 (2) (1995)
Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
Minimal acyclic forbidden minors for the family of graphs with bounded path-width. Discret. Math. 127 (1-3) (1994)
Atsushi Takahashi, Yoji Kajitani
Peel-the-box: a concept of switch-box routing and tractable problems. Integr. 14 (1) (1992)
Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani
Mixed-Searching and Proper-Path-Width. ISA (1991)