A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework.
Yukihide KohiraAtsushi TakahashiPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2008)
Keyphrases
- main contribution
- detection method
- computational complexity
- probabilistic model
- special case
- reduction method
- experimental evaluation
- prior knowledge
- pairwise
- cost function
- dynamic programming
- image processing
- computational cost
- high accuracy
- high speed
- feature space
- detection algorithm
- objective function
- high precision
- bayesian networks