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Yukiko Kubo
Publication Activity (10 Years)
Years Active: 2000-2006
Publications (10 Years): 0
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Publications
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Yukiko Kubo
,
Atsushi Takahashi
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
25 (4) (2006)
Yukiko Kubo
,
Hiroshi Miyashita
,
Yoji Kajitani
,
Kazuyuki Tateishi
Equidistance routing in high-speed VLSI layout design.
Integr.
38 (3) (2005)
Yukiko Kubo
,
Atsushi Takahashi
A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(5) (2005)
Yukiko Kubo
,
Atsushi Takahashi
A global routing method for 2-layer ball grid array packages.
ISPD
(2005)
Yukiko Kubo
,
Hiroshi Miyashita
,
Yoji Kajitani
,
Kazuyuki Tateishi
Equidistance routing in high-speed VLSI layout design.
ACM Great Lakes Symposium on VLSI
(2004)
Yukiko Kubo
,
Shigetoshi Nakatake
,
Yoji Kajitani
,
Masahiro Kawakita
An Incremental Wiring Algorithm for VLSI Layout Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(5) (2003)
Yukiko Kubo
,
Shigetoshi Nakatake
,
Yoji Kajitani
,
Masahiro Kawakita
Chip size estimation based on wiring area.
APCCAS (2)
(2002)
Shigetoshi Nakatake
,
Yukiko Kubo
,
Yoji Kajitani
Consistent floorplanning with hierarchical superconstraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
21 (1) (2002)
Yukiko Kubo
,
Shigetoshi Nakatake
,
Yoji Kajitani
,
Masahiro Kawakita
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts.
VLSI Design
(2002)
Shigetoshi Nakatake
,
Yukiko Kubo
,
Yoji Kajitani
Consistent floorplanning with super hierarchical constraints.
ISPD
(2001)
Yukiko Kubo
,
Yasuhiro Takashima
,
Shigetoshi Nakatake
,
Yoji Kajitani
Self-reforming routing for stochastic search in VLSI interconnection layout.
ASP-DAC
(2000)