Yasuhiro Takashima

Publication Activity (10 Years)

Years Active: 1996-2021
Publications (10 Years): 10

Top Topics

Randomized Algorithm

Theoretical And Experimental Analysis

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Yasuhiro Takashima, Yuichi Nakamura
Theoretical and Experimental Analysis of Traveling Salesman Walk Problem. APCCAS (2021)
Tomohiro Takahashi, Yasuhiro Takashima
Fast Approximate Algorithm for the Single Source Shortest Path with Lazy Update. NGCAS (2018)
Ryota Tsuchihashi, Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura
Task Allocation and Scheduling Optimization in the Heterogeneous Core System. NGCAS (2018)
Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen
A multi-functional memory unit with PLA-based reconfigurable decoder. ReConFig (2016)
Tieyuan Pan, Li Zhu, Lian Zeng, Takahiro Watanabe, Yasuhiro Takashima
An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Komei Nomura, Yasuhiro Takashima, Yuichi Nakamura
PEVaS: Power and execution-time variation-aware scheduling for MPSoC. NEWCAS (2016)
Tieyuan Pan, Lian Zeng, Yasuhiro Takashima, Takahiro Watanabe
A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeffrey Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo
7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory. ISSCC (2016)
Yasuhiro Takashima
Analytical placement for rectilinear blocks. ASP-DAC (2015)
Masato Inagi, Yuichi Nakamura, Yasuhiro Takashima, Shin'ichi Wakabayashi
Inter-FPGA Routing for Partially Time-Multiplexing Inter-FPGA Signals on Multi-FPGA Systems with Various Topologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Tieyuan Pan, Ran Zhang, Yasuhiro Takashima, Takahiro Watanabe
A randomized algorithm for the fixed-length routing problem. APCCAS (2014)
Masatsugu Hosoki, Seiya Nagatsuka, Yasuhiro Takashima
Delay estimation method for correlated net delay variations. APCCAS (2014)
Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima
An Effective Overlap Removable Objective for Analytical Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2013)
Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima
An acceleration method by GPGPU for analytical placement using quasi-Newton method. ASICON (2013)
Seiya Nagatsuka, Yasuhiro Takashima
Sub-path delay estimation for reconvergent path. APCCAS (2012)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
Globally Optimal Time-multiplexing of Inter-FPGA Connections for Multi-FPGA Prototyping Systems. IPSJ Trans. Syst. LSI Des. Methodol. 3 (2010)
Takanobu Shiki, Yasuhiro Takashima, Yuichi Nakamura
Delay analysis of sub-path on fabricated chips by several path-delay tests. ISCAS (2010)
Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa, Tomoharu Tanaka, Mase Taub, Darshak Udeshi, Sjigekazu Yamada, Hiroyuki Yokoyama
32Gb MLC NAND flash memory in 34nm CMOS. ISSCC (2009)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura
Globally optimal time-multiplexing in inter-FPGA connections for accelerating multi-FPGA systems. FPL (2009)
Yuko Hashizume, Yasuhiro Takashima, Yuichi Nakamura
Post-Silicon Clock-Timing Tuning Based on Statistical Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2008)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. ISCAS (2008)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2008)
Shuting Li, Tan Yan, Yasuhiro Takashima, Hiroshi Murata
Fast wire length estimation in obstructive block placement. ICECS (2008)
Tan Yan, Shuting Li, Yasuhiro Takashima, Hiroshi Murata
A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks. ASP-DAC (2007)
Kunihiko Yanagibashi, Yasuhiro Takashima, Yuichi Nakamura
A Relocation Method for Circuit Modifications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
A Performance-Driven Circuit Bipartitioning Method Considering Time-Multiplexed I/Os. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2007)
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
The Oct-Touched Tile: A New Architecture for Shape-Based Routing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2006)
Tan Yan, Qing Dong, Yasuhiro Takashima, Yoji Kajitani
How does partitioning matter for 3D floorplanning? ACM Great Lakes Symposium on VLSI (2006)
Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Yoji Kajitani
A performance-driven circuit bipartitioning algorithm for multi-FPGA implementation with time-multiplexed I/Os. FPT (2006)
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
The oct-touched tile: a new architecture for shape-based routing. ACM Great Lakes Symposium on VLSI (2005)
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
Abstraction and optimization of consistent floorplanning with pillar block constraints. ASP-DAC (2004)
Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake
A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. ISCAS (4) (2004)
Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
Multi-level placement with circuit schema based clustering in analog IC layouts. ASP-DAC (2004)
Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
A device-level placement with multi-directional convex clustering. ACM Great Lakes Symposium on VLSI (2004)
Yasuhiro Takashima, Akira Kaneko, Shinji Sato, Mineo Kaneko
Two-dimensional placement method based on divide-and-replacement. APCCAS (2) (2002)
Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC (2000)
Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani
Detailed-Routability of FPGAs with Extremal Switch-Block Structures. ED&TC (1996)