Shigetoshi Nakatake

Publication Activity (10 Years)

Years Active: 1994-2020
Publications (10 Years): 28

Top Topics

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Xuncheng Zou, Shigetoshi Nakatake
A Fully Synthesizable, 0.3V, 10nW Rail-to-rail Dynamic Voltage Comparator. MWSCAS (2020)
Chao Geng, Qingji Sun, Shigetoshi Nakatake
An Analog CMOS Implementation for Multi-layer Perceptron With ReLU Activation. MOCAST (2020)
Chao Geng, Qingji Sun, Shigetoshi Nakatake
Implementation of Analog Perceptron as an Essential Element of Configurable Neural Networks. Sensors 20 (15) (2020)
Xinghuai Zhang, Shigetoshi Nakatake
On-chip resistance configuration by subthreshold MOSFET-array for ultra weak current sensing. APCCAS (2019)
Ryosuke Sakai, Shigetoshi Nakatake
An Impedance Measurement of Intravesical Urine Volume Appropriate to Seated Posture. APCCAS (2019)
Xuncheng Zou, Shigetoshi Nakatake
A Low Voltage Stochastic Flash ADC without Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2019)
Chao Geng, Bo Liu, Shigetoshi Nakatake
Density Optimization for Analog Layout Based on Transistor-Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2019)
Bo Liu, Gong Chen, Bo Yang, Shigetoshi Nakatake
Routable and Matched Layout Styles for Analog Module Generation. ACM Trans. Design Autom. Electr. Syst. 23 (4) (2018)
Kenya Kondo, Koichi Tanno, Hiroki Tamura, Shigetoshi Nakatake
Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2018)
Takaaki Shirakawa, Ryosuke Sakai, Shigetoshi Nakatake
On-chip Impedance Evaluation with Auto-calibration based on Auto-balancing Bridge. MWSCAS (2018)
Chao Geng, Shigetoshi Nakatake
Hierarchical Floorplanning Based on Analog Structure Tree. NGCAS (2018)
Xuncheng Zou, Shigetoshi Nakatake
Analog Retargeting Constraint Extraction Based on Fundamental Circuits and Layout Regularity. NGCAS (2018)
Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake
Analog perceptron circuit with DAC-based multiplier. Integr. 63 (2018)
Daishi Isogai, Bo Liu, Yoritaka Ishiguchi, Shigetoshi Nakatake
Analog Characterization Module with Data Converter-Coupled Signal Reconfiguration. NGCAS (2017)
Chao Geng, Bo Liu, Shigetoshi Nakatake
Explicit layout pattern density controlling based on transistor-array-style. MWSCAS (2017)
Xuncheng Zou, Bo Liu, Shigetoshi Nakatake
Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit. ACM Great Lakes Symposium on VLSI (2017)
Myung-Chul Kim, Shih-Hsu Huang, Rung-Bin Lin, Shigetoshi Nakatake
Overview of the 2017 CAD contest at ICCAD: Invited paper. ICCAD (2017)
Yoritaka Ishiguchi, Daishi Isogai, Takuma Osawa, Shigetoshi Nakatake
A Perceptron Circuit with DAC-Based Multiplier for Sensor Analog Front-Ends. NGCAS (2017)
Nobuyuki Yahiro, Bo Liu, Atsushi Nanri, Shigetoshi Nakatake, Yasuhiro Takashima, Gong Chen
A multi-functional memory unit with PLA-based reconfigurable decoder. ReConFig (2016)
Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake, Masaya Shimoyama, Masashi Miyagawa, Ryoichi Miyauchi, Koichi Tanno, Akihiro Yamada
Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2016)
Gong Chen, Toru Fujimura, Qing Dong, Shigetoshi Nakatake, Bo Yang
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. ACM Trans. Design Autom. Electr. Syst. 21 (3) (2016)
Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim, Shigetoshi Nakatake
Overview of the 2016 CAD contest at ICCAD. ICCAD (2016)
Chooi-Ling Goh, Shigetoshi Nakatake
A Sensor-Based Data Visualization System for Training Blood Pressure Measurement by Auscultatory Method. IEICE Trans. Inf. Syst. (4) (2016)
Bo Liu, Shigetoshi Nakatake, Bo Yang, Gong Chen
Twin-row-style for MOS analog layout. ICECS (2016)
Gong Chen, Bo Liu, Shigetoshi Nakatake, Bo Yang
Routability of twisted common-centroid capacitor array under signal coupling constraints. MWSCAS (2016)
Takuya Hirata, Ryuta Nishino, Shigetoshi Nakatake, Masaya Shimoyama, Masashi Miyagawa, Koichi Tanno, Akihiro Yamada
Subblock-level matching layout for analog block-pair and its manufacturability evaluation. ISCAS (2015)
Daijiro Murooka, Yu Zhang, Qing Dong, Shigetoshi Nakatake
Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning. ISVLSI (2015)
Gong Chen, Yu Zhang, Qing Dong, Mingyu Li, Shigetoshi Nakatake
Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake
Structured Analog Circuit and Layout Design with Transistor Array. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Gong Chen, Bo Yang, Yu Zhang, Qing Dong, Shigetoshi Nakatake
A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. ACM Great Lakes Symposium on VLSI (2013)
Yu Zhang, Gong Chen, Qing Dong, Mingyu Li, Shigetoshi Nakatake
Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects. VLSI-SoC (2013)
Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake
A comparator energy model considering shallow trench isolation stress by geometric programming. ISQED (2013)
Yu Zhang, Gong Chen, Bo Yang, Jing Li, Qing Dong, Mingyu Li, Shigetoshi Nakatake
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2013)
Shigetoshi Nakatake
Practicality on placement given by optimality of packing. ISPD (2013)
Yu Zhang, Bo Liu, Bo Yang, Jing Li, Shigetoshi Nakatake
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects. ISQED (2012)
Qing Dong, Bo Yang, Gong Chen, Jing Li, Shigetoshi Nakatake
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. ISQED (2012)
Bo Liu, Bo Yang, Shigetoshi Nakatake
Layout-Aware Variability Characterization of CMOS Current Sources. IEICE Trans. Electron. (4) (2012)
Gong Chen, Bo Yang, Shigetoshi Nakatake, Zhangcai Huang, Yasuaki Inoue
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model. ISCAS (2012)
Kota Shinohara, Mihoko Hidaka, Jing Li, Qing Dong, Bo Yang, Shigetoshi Nakatake
Layout-aware variation evaluation of analog circuits and its validity on op-amp designs. ACM Great Lakes Symposium on VLSI (2011)
Bo Liu, Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. ISQED (2011)
Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake
D-A converter based variation analysis for analog layout design. ASP-DAC (2010)
Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake
Structured analog circuit design and MOS transistor decomposition for high accuracy applications. ICCAD (2010)
Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki
Regularity-Oriented Analog Placement with Conditional Design Rules. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Jing Li, Bo Yang, Qing Dong, Shigetoshi Nakatake
Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path. ISCAS (2010)
Kokoro Kato, Masakazu Endo, Tadao Inoue, Shigetoshi Nakatake, Masaki Yamabe, Sunao Ishihara
Photomask Data Prioritization Based on VLSI Design Intent and Its Utilization for Mask Manufacturing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki
Regularity-oriented analog placement with diffusion sharing and well island generation. ASP-DAC (2010)
Jing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake
STI stress aware placement optimization based on geometric programming. ACM Great Lakes Symposium on VLSI (2009)
Qing Dong, Shigetoshi Nakatake
Structured Placement with Topological Regularity Evaluation. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
Incremental buffer insertion and module resizing algorithm using geometric programming. ACM Great Lakes Symposium on VLSI (2009)
Qing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake
Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Bo Yang, Shigetoshi Nakatake
Fast Shape Optimization of Metalization Patterns for Power-MOSFET Based Driver. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Bo Yang, Shigetoshi Nakatake, Hiroshi Murata
Fast Shape Optimization of Metallization Patterns for DMOS Based Driver. ISQED (2008)
Qing Dong, Shigetoshi Nakatake
Constraint-free analog placement with topological symmetry structure. ASP-DAC (2008)
Toru Fujimura, Shigetoshi Nakatake
Transistor-level programmable MOS analog IC with body biasing. ISCAS (2008)
Bo Yang, Hiroshi Murata, Shigetoshi Nakatake
A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2008)
Shigetoshi Nakatake
Structured Placement with Topological Regularity Evaluation. ASP-DAC (2007)
Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh
Block placement to ensure channel routability. ACM Great Lakes Symposium on VLSI (2007)
Keiji Kida, Takehiko Matsuo, Tetsuya Tashiro, Shigetoshi Nakatake
Sequence-Pair Based Compaction under Equi-Length Constraint. APCCAS (2006)
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
The Oct-Touched Tile: A New Architecture for Shape-Based Routing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2006)
Takashi Nojima, Nobuto Ono, Shigetoshi Nakatake, Toru Fujimura, Koji Okazaki, Yoji Kajitani
Adaptive Porting of Analog IPs with Reusable Conservative Properties. ISVLSI (2006)
Ning Fu, Mitsutoshi Mineshima, Shigetoshi Nakatake
Multi-SP: A Representation with United Rectangles for Analog Placement and Routing. ISVLSI (2006)
Tan Yan, Shigetoshi Nakatake, Takashi Nojima
Formulating the Empirical Strategies in Module Generation of Analog MOS Layout. ISVLSI (2006)
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
The oct-touched tile: a new architecture for shape-based routing. ACM Great Lakes Symposium on VLSI (2005)
Ning Fu, Shigetoshi Nakatake, Yasuhiro Takashima, Yoji Kajitani
Abstraction and optimization of consistent floorplanning with pillar block constraints. ASP-DAC (2004)
Keiji Kida, Xiaoke Zhu, Changwen Zhuang, Yasuhiro Takashima, Shigetoshi Nakatake
A fast algorithm for crosspoint assignment under crosstalk constraints with shielding effects. ISCAS (4) (2004)
Takashi Nojima, Xiaoke Zhu, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
Multi-level placement with circuit schema based clustering in analog IC layouts. ASP-DAC (2004)
Takashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
A device-level placement with multi-directional convex clustering. ACM Great Lakes Symposium on VLSI (2004)
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
An Incremental Wiring Algorithm for VLSI Layout Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2003)
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
Chip size estimation based on wiring area. APCCAS (2) (2002)
Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
Consistent floorplanning with hierarchical superconstraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (1) (2002)
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. VLSI Design (2002)
Shigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani
Consistent floorplanning with super hierarchical constraints. ISPD (2001)
Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake
Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. VLSI Design (2000)
Yukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani
Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC (2000)
Keishi Sakanushi, Shigetoshi Nakatake, Yoji Kajitani
The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks. ICCAD (1998)
Shigetoshi Nakatake, Keishi Sakanushi, Yoji Kajitani, Masahiro Kawakita
The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications. ICCAD (1998)
Shigetoshi Nakatake, Masahiro Furuya, Yoji Kajitani
Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear Modules. ASP-DAC (1998)
Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
Module packing based on the BSG-structure and IC layout applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (6) (1998)
Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (12) (1996)
Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani
Module placement on BSG-structure and IC layout applications. ICCAD (1996)
Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani
Rectangle-packing-based module placement. ICCAD (1995)
Shigetoshi Nakatake, Yoji Kajitani
Channel-driven global routing with consistent placement (extended abstract). ICCAD (1994)